m3488q1 STMicroelectronics, m3488q1 Datasheet - Page 13

• Manufacturer Part Number: m3488q1
• Description: 256 X 256 Digital Switching Matrix
• Manufacturer: STMicroelectronics

During a very long internal operation (device initiali-
zation after RESET going high or execution of in-
struction 6) a new set of data bytes with a valid op-
code is accepted while a wrong code is rejected. At
the end of the current routine execution takes place
in the same way as described before.
At the end of an instruction it is normally recom-
mended to read one or both registers. To exploit in-
struction 6, however, it is mandatoryto read register
OR2. This is because instruction 6, used between
other short instructions of type 1 to 5, must have pri-
ority and can be enabled only after the short instruc-
tions have been completed. Instruction 6 normally
has a long process and a special flow which is de-
scribed below.
First a not-all-zero mask is stored in the ”expected
messages” register and in another ”background”
register. This operation starts the second phase of
instruction 6 which is called ”channel 0 extraction”
and is repeated at the beginning of any new time
frame.At the beginningof the time frame a new copy
of activated channels to be extracted is made from
the ”background register” and put in the ”expected
messages” register. In addition the latter register is
modified to indicate the exact number of messages
that have arrived. The term messages covers any
input 0 channeldata with startingsequencedifferent
from the label 01. So using this label the number of
expected messages can be reduced to correspond
to the number of effective messages. If and only if
the residual number is different from zero will the de-
INSTRUCTION 1: CHANNEL CONNECTION
Match C/D CS
yes/no
yes
yes
X
X
X
x
Control Signals
0
0
0
0
1
0
1
0
0
0
0
0
0
0
WR RD
0
0
0
0
0
1
1
1
1
1
1
1
0
0
(Bo2
(Bo2
(Bi2
D7
C7
A7
(1
X
X
X
X
X
Bo1
Bo1
Bi1
D6
C6
A6
X
X
X
X
X
1
Bo0
Bo0
D5
C5
Bi0
A5
X
X
X
X
X
1
Data Bus
Co4 Co3 Co2 Co1 Co0 4th Data Byte: selected output channel.
Ci4
Ci4
D4
C4
C8
X
X
X
1
1
0
Ci3
Ci3
D3
C3
X
X
0
1
0
0
0
Bo2 Bo1 Bo0 3
Ci2
Ci2
D2
Bi2
C2
vice start the extraction protocol at the end of the
current routine.
The procedureis as follows : the DR outputis pulsed
low as a two cycle interrupt request and OR2 is
loaded with the total number of active channels to
be extracted.
The transfer of OR2 content to the microprocessor
continues the extraction which consists of repeated
steps of OR1 and OR2 loading, indicating respec-
tively the message and the incoming bus number.
Reading the registers in the order OR1, OR2 must
be continued until completion or until the time frame
runs out.
With a new time frame a new extraction process be-
gins, resuming the copy operation from the back-
ground register.
During extraction the active channels are scanned
from the highest to the lowest number (from 7 to 0).
While extraction is being carried out the time interval
requirements between active rising edges of RD are
minimum 4 to 7 t
minimum 2 times t
details are given in the following tables.
INSTRUCTION TABLES
The most significant digits of OR2 A7, A6, A5 are a
copy of the PCM selected output bus ; the least sig-
nificant digits of OR2 are the opcode, C8 is the con-
trol bit. In any case parentheses() define actual reg-
ister content.
0
1
0
0
0
Bi1
Ci1
Ci1
D1
C1
0
1
0
0
0
Ci0)
Ci0
D0
Bi0
C0
1)
1)
1)
1
1
1
2
Instruction Opcode
OR1: CM content copy, that is,
for mismatch condition,
for match condition
OR2: that is,
for mismatch condition
for match condition
st
nd
rd
CK
CK
Data Byte: selected input bus.
Data Byte: selected output bus.
Data Byte: selected input channel.
for sequenceOR1 - OR2. More
for sequence OR2 - OR1 and
Notes
M3488
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