adc-305 C&D Technologies., adc-305 Datasheet - Page 3

• Manufacturer Part Number: adc-305
• Description: 8-bit, 20mhz Cmos A/d Converters
• Manufacturer: C&D Technologies.

External Reference Mode
5. Logic inputs are CMOS compatible. Normally a series 74HC
6. The start convert (A/D CLK) pulse can be a 50% duty cycle
These values may differ from one device to another. Voltage
changes on the +5V supply have a direct influence on the
performance of the device. The use of external references is
recommended for applications sensitive to gain error.
Tie V
input voltage range. The reference resistance between V
and V
output impedance of the reference source small enough
while, at the same time, keeping sufficient drive capacity.
Insert a 0.1µF bypass ceramic chip capacitor between V
and GND to minimize the effect of the 20MHz clock
running nearby. See Figure 5.
is used as a driver. It is recommended to pull up to +5V if
the device is driven with TTL.
clock. Both T
®
RB
RT
to AGND, and apply +2V to V
is about 300 ohms. It is important to make the
PW1
ANALOG
OUTPUT
CLOCK
INPUT
DATA
and T
Digital Output Circuit, Bit1 through Bit 8
+DV
+DGND
V
RT
17
PW0
Voltage Reference (V
S
T
®
PW1
AGND
Equivalent Circuit
are 25ns minimum. A slightly
+AV
S
T
N
PW0
N-3
Ta
RT
RT
,V
to use at 0 to +2V
Td= 30ns max.
V
RB
23
RB
)
Figure 3. Equivalent Circuits
Figure 2. Timing Diagram
N+1
N-2
output pins turn to high impedance.
Equivalent Circuit for OE and A/D CLK
OE - Low data is output when high digital
A/D CLK
OE
22
RT
when shorted with V
RB
V
Generates +0.6V
RBS
3
AGND
7. The digital data outputs are 3-state and TTL compatible. To
8. Maximum 30ns (18ns typical) after the rising edge of the
9. The 20MHz sampling rate is guaranteed. It is not
+DV
DGND
longer T
frequency input signals.
enable the 3-state outputs, connect the OUTPUT ENABLE
(pin 1) to GND. To disable, connect it to +5V. It is
recommended that the data outputs be latched and buffered
through output registers.
Nth conversion pulse, the result of the (N-3) conversion can
be obtained. Data is stored firmly in an output register, such
as an 74LS574, using the rising edge of a start convert
pulse as a trigger. The (N–4) data is stored in this case. See
the timing diagrams, Figure 2 and 4.
recommended to use this device at sampling rates slower
than 500kHz because the droop characteristics of the
internal sample and holds will then exceed the limit
required to maintain the specified accuracy of the device.
S
N+2
N-1
B
PW1
will improve linearity of the system for higher
V
19
IN
N+3
AGND
N
16
when shorted with V
Generates +2.6V
V
+AV
RTS
Analog Input
S
+AV
N+4
N+1
T
S
ADC-305