h5ps1g83nfr Hynix Semiconductor, h5ps1g83nfr Datasheet - Page 14

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h5ps1g83nfr

Manufacturer Part Number
h5ps1g83nfr
Description
1gb Ddr2 Sdram
Manufacturer
Hynix Semiconductor
Datasheet

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h5ps1g83nfr-S6C
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Rev. 0.1 / Feb. 2010
3.3.3 OCD default characteristics
Note :
Output impedance
Output impedance step size for OCD calibration
Pull-up and pull-down mismatch
Output slew rate
1. Absolute Specifications ( Toper; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
2. Impedance measurement condition for output source dc current: VDDQ=1.7V; VOUT=1420mV; (VOUT-
3. Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
4. Slew rate measured from vil(ac) to vih(ac).
5. The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as
6. This represents the step size when the OCD is near 18 ohms at nominal conditions across all process
8. Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in
7. DRAM output slew rate specification applies to 400, 533 and 667 MT/s speed bins.
VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be
less than 23.4 ohms for values of VOUT between 0V and 280mV.
measured from AC to AC. This is guaranteed by design and characterization.
corners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved
if the OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.
Output Slew rate load:
tDQSQ and tQHS specification.
Description
Output
(Vout)
VTT
25 ohms
Parameter
Sout
Reference
point
1.5
Min
0
0
-
Nom
-
-
1.5
Max
4
5
-
H5PS1G83NFR
ohms
ohms
ohms
V/ns
Unit
1,4,5,6,7,8
1,2,3
Notes
1
6
14

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