ta1317afg TOSHIBA Semiconductor CORPORATION, ta1317afg Datasheet - Page 51

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ta1317afg

Manufacturer Part Number
ta1317afg
Description
Deflection Processor Ic For Tv
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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Note
No.
41
Vertical ramp cut level
Parameter
SW6
ON
SW7
A
SW8
OFF
SW10
Test Condition
OFF
SW Mode
SW13
B
SW14
ON
SW21
51
A
SW30
A
(2) Set VD (sub-address: 00) to DC-Coupling mode (data: 80).
(3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 8F).
(4) Set V S CORRECTION (sub-address: 09) to center (data: A0).
(5) Measure amplitudes V
(6) Set V-RAMP to maximum and measure amplitudes V
(7) Calculate cut levels using the following formulas.
Pin 7
(V NF) waveform
Pin 7
(V NF) waveform
(1) Input vertical trigger pulse to pin V
Pulse level (VT) = 3.0 V
V
V
(unless otherwise specified, V
CHH
CLH
=
=
Sub-address 04 data: 87
Sub-address 05 data: 81
V
V
T
B
V
− V
V
− V
B
T
TH
BH
T
and V
× 100
× 100
B
CC
as shown in the figure below.
Test Method
10 ms
IN
10 ms
= 9 V, Ta = 25 ± 3°C, data = preset values)
.
10 ms
10 ms
TH
and V
BH
TA1317AFG
.
2005-08-18

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