m28f010 Intel Corporation, m28f010 Datasheet - Page 5

• Manufacturer Part Number: m28f010
• Description: 1024k 128k X 8 Cmos Flash Memory
• Manufacturer: Intel Corporation

When V
used to access array data to output the intelligent
Identifier codes and to access data for program
erase verification When V
operation can only access the array data
Output Disable
With Output-Enable at a logic-high level (V
from the device is disabled Output pins are placed
in a high-impedance state
Standby
With Chip-Enable at a logic-high level the standby
operation disables most of the M28F010’s circuitry
and substantially reduces device power consump-
tion The outputs are placed in a high-impedance
state independent of the Output-Enable signal
If the M28F010 is deselected during erasure pro-
gramming
device draws active current until the operation is
terminated
intelligent Identifier Operation
The intelligent Identifier operation outputs the manu-
facturer code (89H) and device code (B4H) Pro-
gramming equipment automatically matches the de-
vice with its proper erase and programming algo-
rithms
With Chip-Enable and Output-Enable at a logic low
level raising A9 to high voltage V
operation Data read from locations 0000H and
0001H represent the manufacturer’s code and the
device code respectively
PP
is high (V
or
program erase
PPH
) the read operation can be
PP
is low (V
verification
ID
PPL
activates the
) the read
IH
) output
the
The manufacturer- and device-codes can also be
read via the command register for instances where
the M28F010 is erased and reprogrammed in the
target system Following a write of 90H to the com-
mand register a read from address location 0000H
outputs the manufacturer code (89H) A read from
address 0001H outputs the device code (B4H)
Write
Device erasure and programming are accomplished
via the command register when high voltage is ap-
plied to the V
serve as input to the internal state-machine The
state-machine outputs dictate the function of the
device
The command register itself does not occupy an ad-
dressable memory location The register is a latch
used to store the command along with address and
data information needed to execute the command
The command register is written by bringing Write-
Enable to a logic-low level (V
low Addresses are latched on the falling edge of
Write-Enable while data is latched on the rising
edge of the Write-Enable pulse Standard microproc-
essor write timings are used
The three high-order register bits (R7 R6 R5) en-
code the control functions All other register bits R4
to R0 must be zero The only exception is the reset
command when FFH is written to the register Reg-
ister bits R7 – R0 correspond to data inputs D7– D0
Refer to AC Write Characteristics and the Erase
Programming
parameters
PP
Waveforms
pin The contents of the register
IL
) while Chip-Enable is
for
specific
M28F010
timing
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