m28f010 Intel Corporation, m28f010 Datasheet - Page 11

• Manufacturer Part Number: m28f010
• Description: 1024k 128k X 8 Cmos Flash Memory
• Manufacturer: Intel Corporation

DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory ar-
rays Intel provides two read-control inputs to ac-
commodate multiple memory connections Two-line
control provides for
a the lowest possible memory power dissipation
b complete assurance that output bus contention
To efficiently use these two control inputs an ad-
dress-decoder output should drive chip-enable
while the system’s read signal controls all flash-
memories and other parallel memories This assures
that only enabled memory devices have active out-
puts while deselected devices maintain the low
power standby condition
Power Supply Decoupling
Flash-memory power-switching characteristics re-
quire careful device decoupling System designers
are interested in three supply current (I
standby active and transient current peaks pro-
duced by falling and rising edges of chip-enable The
capacitive and inductive loads on the device outputs
determine the rnagnitudes of these peaks
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks
Each device should have a 0 1 mF ceramic capacitor
connected between V
and V
Place the high-frequency low-inherent-inductance
capacitors as close as possible to the devices Also
for every eight devices a 4 7 mF electrolytic capaci-
tor should be placed at the array’s power supply
connection between V
tor will overcome voltage slumps caused by printed-
circuit-board trace inductance
charge to the smaller capacitors as needed
NOTES
1 Formula to calculate typical Program Program Verify Power
2 Formula to calculate typical Erase Erase Verify Power
3 One Complete Cycle
4 ‘‘Typicals’’ are not guaranteed but based on a limited number of samples from production lots
I
I
and
will not occur
PP2
CC4
Bytes)
SS
typical
typical
Array Program Program Verify
Array Erase Erase Verify
One Complete Cycle
a
a
V
t
WHGL c
CC
Operation
(I
CC3
CC
e
CC
Array Preprogram
I
typical
and V
PP4
Table 4 M28F010 Typlcal Update Power Dissipation
and V
typical)
SS
c
SS
t
ERASE
and between V
and will supply
The bulk capaci-
a
CC
V
typical
a
CC c
) issues
Array Erase
a
Bytes
I
PP
CC5
e
typical
V
a
c
PP
Notes
V
Programming flash-memories while they reside in
the target system requires that the printed circuit
board designer pay attention to the V
ply trace The V
rent for programming Use similar trace widths and
layout considerations given the V
equate V
crease V
Power Up Down Protection
The M28F010 is designed to offer protection against
accidental erasure or programming during power
transitions Upon power-up the M28F010 is indiffer-
ent as to which power supply V
up first Power supply sequencing is not required In-
ternal circuitry in the M28F010 ensures that the
command register is reset to the read mode on pow-
er up
A system designer must guard against active writes
for V
Since both WE and CE must be low for a command
write driving either to V
trol register architecture provides an added level of
protection since alteration of memory contents only
occurs after successful completion of the two-step
command sequences
M28F010 Power Dissipation
When designing portable systems designers must
consider battery power consumption not only during
device operation but also for data retention during
system idle time Flash nonvolatility increases the
usable battery life of your system because the
M28F010 does not consume any power to retain
code or data when the system is off Table 4 illus-
trates the power dissipated when updating the
M28F010
e
typical
Program
(V
PP
1
2
3
PP3
c
V
PP c
CC
Trace on Printed Circuit Boards
t
WHGL c
typical
Prog Pulses (t
voltages above V
PP
PP
voltage spikes and overshoots
supply traces and decoupling will de-
Bytes
c
t
PP
ERASE
Bytes)
c
pin supplies the memory cell cur-
WHWH1 c
typical
typical
IH
(4)
Power Dissipation
(Watt-Seconds)
will inhibit writes The con-
LKO
a
Prog Pulses (t
I
0 171
0 136
0 478
I
CC2
when V
PP5
PP
CC
typical
typical
or V
power bus Ad-
PP
PP
CC
power sup-
M28F010
a
c
is active
WHWH1 c
t
t
WHGL c
WHGL c
powers
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