k6f2008v2e Samsung Semiconductor, Inc., k6f2008v2e Datasheet - Page 8
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k6f2008v2e
Manufacturer Part Number
k6f2008v2e
Description
256kx8 Bit Super Low Power And Low Voltage Full Cmos Static Ram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K6F2008V2E.pdf
(9 pages)
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K6F2008V2E Family
DATA RETENTION WAVE FORM
CS
CS
TIMING WAVEFORM OF WRITE CYCLE(3)
1
Address
CS
CS
WE
Data in
Data out
V
3.0V
2.2V
V
CS
GND
2
V
3.0V
CS
V
0.4V
GND
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS
2. t
3. t
4. t
CC
DR
CC
DR
controlled
controlled
CS
t
WP
CW
AS
WR
1
2
1
2
2
is measured from the address valid to the beginning of write.
is measured from the begining of write to the end of write.
is measured from the CS
is measured from the end of write to the address change.
going high and WE going low : A write end at the earliest transition among CS
1
going low or CS
High-Z
t
SDR
t
t
SDR
AS(3)
1
, a high CS
2
going high to the end of write.
(CS
2
2
Controlled)
and a low WE. A write begins at the latest transition among CS
Data Retention Mode
Data Retention Mode
t
AW
8
CS
t
t
WC
CS
CW(2)
t
WP(1)
1
2
V
CC
0.2V
- 0.2V
t
1
DW
going high, CS
Data Valid
t
WR(4)
t
DH
2
going low and WE going high,
t
RDR
High-Z
t
RDR
CMOS SRAM
1
goes low,
Revision 1.1
May 2003