m62320gp Renesas Electronics Corporation., m62320gp Datasheet - Page 5

• Manufacturer Part Number: m62320gp
• Description: 8-bit I/o Expander For I2c Bus
• Manufacturer: Renesas Electronics Corporation.

M62320GP
Functional Blocks
I
The I
SDA, SCL, CS0, CS1 and CS2 signals and then the latch pulses, dedicated to each data latch are generated.
Data Latch
This IC has 3 types of data latch: the I/O setting data latch, the input data latch and the output data latch and each latch
is controlled by the I
• I/O setting data latch
• Output data latch
• Input data latch
Parallel Input/Output Port
In case I/O setting latch is set to low (the input mode), each parallel terminal becomes hi-impedance and is able to
accept an input. In another case I/O setting latch is set to high (output mode), each parallel terminal output a data
according to the state of the output data latch.
Power on Reset
When power is turned on, each latch is reset and then the parallel data I/O terminals become hi-impedance (input mode).
REJ03D0909-0100 Rev.1.00 Mar 25, 2008
Page 5 of 10
2
C BUS Interface
These latches set input- or output-state of each parallel data terminals (D0 to D7). They are set at the next byte after
receiving the slave address byte in the write mode from the master. In case this latch is set to high, the data is
transferred from the I
data terminals to the I
In the write mode, the data from the I
output data after a setting in write mode, the output data is taken into the latches.
In the read mode, the data of parallel data terminals is latched in the input data latches. The input data is taken into
the latches from the parallel data terminals on every 8th negative edge of SCL clock. The latched data is output to
the master through the sift resistor. On the output terminal assigned by the I/O setting latch, the input data latch
takes the state of the output terminal.
2
C BUS interface recognizes start/stop conditions, a slave address and a write/read mode selection by receiving
2
C BUS interface.
2
2
C BUS interface to the parallel data terminals. In the opposite transmission: from the parallel
C BUS, it is set to low.
2
C BUS to the parallel data terminals is latched. When the master transmits