km29u128t Samsung Semiconductor, Inc., km29u128t Datasheet - Page 4

• Manufacturer Part Number: km29u128t
• Description: 16m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

PRODUCT INTRODUCTION
KM29U128T, KM29U128IT
The KM29U128 is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows by 528 columns. Spare sixteen columns are
located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans-
fer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells
that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32
pages formed by one NAND structures, totaling 8448 NAND structures of 16 cells. The array organization is shown in Figure 2. The
program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory
array consists of 1024 separately erasable 16K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the
KM29U128.
The KM29U128 has addresses multiplexed into 8 I/O s. This scheme dramatically reduces pin counts and allows systems upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O s by
bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus cycle except
for Block Erase command which requires two cycles: one cycle for erase-setup and another for erase-execution after block address
loading. The 16M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column
address, low row address and high row address, in that order. Page Read and Page Program need the same three address cycles
following the required command input. In Block Erase operation, however, only the two row address cycles are used. Device opera-
tions are selected by writing specific commands into the command register. Table 1 defines the specific commands of the
KM29U128.
Table 1. COMMAND SETS
NOTE : 1. The 00H command defines starting address of the 1st half of registers.
Sequential Data Input
Read 1
Read 2
Read ID
Reset
Page Program
Block Erase
Read Status
2. The 50h command is valid only when the SE(pin 6) is low level.
The 01H command defines starting address of the 2nd half of registers.
After data access on the 2nd half of register by the 01h command, the status pointer is
automatically moved to the 1st half register(00h) on the next cycle.
Function
1st. Cycle
00h/01h
50h
80h
90h
FFh
10h
60h
70h
(2)
(1)
4
2nd. Cycle
D0h
-
-
-
-
-
-
-
Acceptable Command during Busy
FLASH MEMORY
O
O