adv473 Analog Devices, Inc., adv473 Datasheet - Page 6

• Manufacturer Part Number: adv473
• Description: Cmos 135 Mhz True-color Graphics Triple 8-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

ADV473
TERMINOLOGY
BLANKING LEVEL
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
COLOR VIDEO (RGB)
This usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
COMPOSITE SYNC SIGNAL (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
COMPOSITE VIDEO SIGNAL
The video signal with or without setup, plus the composite
SYNC signal.
GRAY SCALE
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different lev-
els while a 6-bit DAC contains 64.
RASTER SCAN
The most basic method of sweeping a CRT one line at a time to
generate and to display images.
REFERENCE BLACK LEVEL
The maximum negative polarity amplitude of the video signal.
REFERENCE WHITE LEVEL
The maximum positive polarity amplitude of the video signal.
SETUP
The difference between the reference black level and the blank-
ing level.
SYNC LEVEL
The peak level of the composite SYNC signal.
VIDEO SIGNAL
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
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CIRCUIT DESCRIPTION
MPU Interface
The ADV473 supports a standard MPU bus interface, allowing
the MPU direct access to the color palette RAM and overlay
color registers.
Three address decode lines, RS0–RS2, specify whether the
MPU is accessing the address register, the color palette RAM,
the overlay registers, or read mask register. These controls also
determine whether this access is a read or write function. Table
I illustrates this decoding. The 8-bit address register is used to
address the contents of the color palette RAM and overlay
registers.
RS2
0
0
0
0
1
1
1
1
Color Palette Writes
The MPU writes to the address register (selecting RAM write
mode, RS2 = 0, RS1 = 0 and RS0 = 0) with the address of the
color palette RAM location to be modified. The MPU performs
three successive write cycles (8 or 6 bits each of red, green, and
blue), using RS0–RS2 to select the color palette RAM (RS2 =
0, RS1 = 0, RS0 = 1). After the BLUE write cycle, the three
bytes of color information are concatenated into a 24-bit word
or an 18-bit word and written to the location specified by the
address register. The address register then increments to the
next location which the MPU may modify by simply writing an-
other sequence of red, green, and blue data. A complete set of
colors can be loaded into the palette by initially writing the start
address and then performing a sequence of RED, GREEN and
BLUE writes. The address automatically increments to the next
highest location after a BLUE write.
Color Palette Reads
The MPU writes to the address register (selecting RAM read
mode, RS2 = 0, RS1 = 1 and RS0 = 1) with the address of the
color palette RAM location to be read back. The contents of the
palette RAM are copied to the RED, GREEN and BLUE regis-
ters and the address register increments to point to the next pal-
ette RAM location. The MPU then performs three successive
read cycles (8 or 6 bits each of red, green, and blue), using
RS0–RS2 to select the color palette RAM (RS2 = 0, RS1 = 0,
RS0 = 1). After the BLUE read cycle, the 24/18 bit contents of
the palette RAM at the location specified by the address register
is loaded into the RED, GREEN and BLUE registers. The ad-
dress register then increments to the next location which the
MPU can read back by simply reading another sequence of red,
green, and blue data. A complete set of colors can be read back
from the palette by initially writing the start address and then
performing a sequence of RED, GREEN and BLUE reads. The
address automatically increments to the next highest location
after a BLUE read.
RS1
0
1
0
1
0
1
0
1
Table I. Control Input Truth Table
RS0
0
1
1
0
0
1
1
0
Addressed by MPU
Address Register (RAM Write Mode)
Address Register (RAM Read Mode)
Color Palette RAM
Pixel Read Mask Register
Address Register (Overlay Write Mode)
Address Register (Overlay Read Mode)
Overlay Registers
Command Register
REV. A