adv473 Analog Devices, Inc., adv473 Datasheet - Page 3

• Manufacturer Part Number: adv473
• Description: Cmos 135 Mhz True-color Graphics Triple 8-bit Video Ram-dac
• Manufacturer: Analog Devices, Inc.

Parameter
fmax
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
outputs. Analog output load
2
3
4
5
then extrapolated back to remove the effects of charging the 50 pF capacitor. This means that the times, t
true values for the device and, as such, are independent of external bus loading capacitances.
6
Specifications subject to change without notice.
REV. A
TIMING CHARACTERISTICS
TTL input values are 0 to 3 volts, with input rise/fall times
V
Temperature range (T
t
t
Settling time does not include clock and data feedthrough.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SK
PD
RS0, RS1,
3
5
CR0–CR3
4
4
5
5
AA
(WRITE)
RD, WR
6
and t
and t
(READ)
D0–D7
D0–D7
= 5 V
RS2
Figure 1. MPU Read/Write Timing
4
6
are measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.4 V or 2.4 V.
are derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 3. The measured number is
5%.
VALID
t
1
t
t
t
3
MIN
4
2
to T
135 MHz
Version
135
10
10
3
40
20
5
10
10
100
50
40
2
2
7.4
3
2
30
3
13
2
4
DATA OUT (RD = 0)
10 pF, D0-D7 output load
t
MAX
10
DATA IN (WR = 0)
t
14
); 0 C to +70 C; T
t
7
t
t
9
t
t
8
6
5
110 MHz
Version
110
10
10
3
40
20
5
10
10
100
50
40
3
3
9.1
3.5
3
30
3
13
2
4
1
t
11
t
14
(V
All specifications T
J
(Silicon Junction Temperature)
AA
2
50 pF. See timing notes in Figure 2.
= 5 V; V
3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
OL0-OL3, S0–S1,
NOTES
1. OUTPUT DELAY MEASURED FROM THE 50% POINT OF THE RISING EDGE
2. SETTLING TIME MEASURED FROM THE 50% POINT OF FULL-SCALE
3. OUTPUT RISE/FALL TIME MEASURED BETWEEN THE 10% AND 90%
POINTS OF FULL-SCALE TRANSITION.
R0-R7, G0–G7,
SYNC, BLANK
OF CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
TRANSITION TO THE OUTPUT REMAINING WITHIN 1 LSB.
80 MHz
Version
80
10
10
3
40
20
5
10
10
100
50
40
3
3
12.5
4
4
30
3
13
2
4
IOR, IOG, IOB
REF
Figure 2. Video Input/Output Timing
t
CLOCK
14
B0–B7,
= 1.235 V; R
MIN
to T
–3–
100
t
66 MHz
Version
66
10
10
3
40
20
5
10
10
50
40
3
3
15.15
5
5
30
3
13
2
4
MAX
15
t
L
14
3
t
t
= 37.5 , C
unless otherwise noted.)
100 C .
14
16
DATA
t
t
13
12
Units
MHz
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
ns max
ns max
ns
L
= 10 pF; R
5
and t
t
17
6
, quoted in the timing characteristics are the
SET
t
19
Conditions/Comments
Clock Rate
RS0–RS2 Setup Time
RS0–RS2 Hold Time
RD Asserted to Data Bus Driven
RD Asserted to Data Valid
RD Negated to Data Bus 3-Stated
Read Data Hold Time
Write Data Setup Time
Write Data Hold Time
CR0–CR3 Delay Time
RD, WR Pulse Width Low
RD, WR Pulse Width High
Pixel & Control Setup Time
Pixel & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
Analog Output Rise/Fall Time
Analog Output Settling Time
Analog Output Skew
Pipeline Delay
t
= 140 .
18
Figure 3. Load Circuit for Bus
Access and Relinquish Time
OUTPUT
PIN
TO
50pF
ADV473
3.2mA
400 A
+2.1V