uaa1570hl NXP Semiconductors, uaa1570hl Datasheet - Page 8

• Manufacturer Part Number: uaa1570hl
• Description: Global Positioning System Gps Front-end Receiver Circuit
• Manufacturer: NXP Semiconductors

Philips Semiconductors
1999 May 10
LIMINP
BFCP
V
DATA
V
SIGN
DGND
V
SCLK
PLLGND
P39GND
CCA(LIM)
DDD
CCA(PLL)
Global Positioning System (GPS) front-end
receiver circuit
SYMBOL
PIN
29
30
31
32
33
34
35
36
37
38
39
1.696
1.696
2.7
CMOS level
2.7
(independent
TTL output
0
2.7
1.34
0
0
of V
V
CC
TYPICAL VALUES (V)
CC
= 2.7 V
PIN VOLTAGE
level)
3.999
3.999
5
CMOS level
5
(independent
TTL output
0
5
2.5
0
0
of V
V
CC
CC
= 5 V
level)
Positive limiter input: AC couple this pin to the second IF filter
output or to ground if unused with single-ended filter
applications. The DC voltage is approximately 1 V below the
V
Positive limiter input DC feedback loop decoupling:
AC couple this pin to ground in close proximity to the pin.
The DC voltage is approximately 1 V below the V
on pin 31. No DC coupling.
Limiter, sample clock squaring and sampler Emitter
Coupled Logic (ECL) circuits power supply: decouple in
close proximity to pins 26 and 31. If present, isolate from the
common V
a large decoupling capacitor between this block and the mixers.
Serial interface data input: this DC-coupled CMOS DATA input
accepts 20-bit programming words into the synthesizer data
input register, while the STROBE is LOW, on the rising edge of
the CLOCK input. A DC short-circuit to ground is recommended
with the default frequency plan.
SIGN bit TTL output driver power supply: critically isolate and
separately decouple this digital V
analog (V
decoupling components. Particular attention should be applied to
prevent coupling into V
use the digital supply from the back-end.
Amplitude and time quantized second IF output signal:
extreme care should be taken to isolate this sampled TTL output
signal from all analog traces and components, particularly the
second IF filter components at the limiter input. Avoid coupling
into the reference oscillator signal trace.
SIGN bit TTL output driver sink ground: critically isolate this
digital supply ground from all other analog supplies and grounds.
Maintain minimum trace lengths to decoupling components.
Synthesizer power supply: decouple in close proximity to
pin 38
Sample clock squaring input: accepts LOW-level AC coupled
sample clock inputs directly from the PLL reference oscillator or
DC-coupled externally squared digital clocks derived from the
PLL reference oscillator after external frequency division. The
maximum DC-coupled input level at pin 37 should not exceed
75% of the V
half the supply value on V
PLL ground: minimize ground inductance; use close proximity
decoupling to the V
this pin provides additional RF/IF shielding and has to be
connected to ground
CCA(LIM)
8
supply on pin 31. No DC coupling.
CCA
CC
CCA(LIM)
) supplies. Maintain minimum trace lengths to
line sourcing the first and second mixer by placing
CCA(PLL)
supply value. The threshold level is set at
CCA(LIM)
DESCRIPTION
CCA(LIM)
supply pin 36
pin 31. If SAA1575HL is used,
DDD
pin 31.
supply from all other
UAA1570HL
Product specification
CCA(LIM)
supply