r8a66120ffa Renesas Electronics Corporation., r8a66120ffa Datasheet - Page 3

• Manufacturer Part Number: r8a66120ffa
• Description: 4m-bit X 2 Multiple Field Memory
• Manufacturer: Renesas Electronics Corporation.

REJ03F0161-0170 Rev.1.70 May.16.2008
R8A66120FFA
page 3 of 14
Mode pin Setting
Operation Description
Pin Function Description
In normal operation mode. It should be fixed on "L".
CKA
WEA
DB<3:0>
CKB
WRESB
WEB
DA<3:0>
WRESA
TEST<2:1>
*Note1: X of the pin name shows A or B. A = A-system, B = B-system.
Pin name
Qx<3:0>
Dx<3:0>
WRESx
RRESx
MODE
POR
GND
WEx
CKx
REx
Vcc
(*1)
4
4
Pin Name
MODE
H
L
1024K-w
1024K-w
FIFO(A)
FIFO(B)
Clock input
Write enable input
Write reset input
Read enable input
Read reset input
Data input
Data output
Mode setting input
Test setting input
Power on reset input
Power supply pin
Ground pin
4-bit
4-bit
X
X
Name
4
4
Out of a guarantee
Normal operation
Operation MODE
REB
QA<3:0>
RRESA
REA
QB<3:0>
RRESB
Output
Output
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
-
-
Number of
pin(s)
R8A66120FFA can be controlled two pieces of 1024K-word x 4-bit
FIFO completely independently. Taking FIFO (A) as an example,
the operation of FIFO memory is described as follows.
The operation of FIFO (B) is the same as that of FIFO (A).
When write enable input WEA is "L", the contents of data input DA<3:0>
are written into FIFO (A) in synchronization with the rising of clock input
CKA.
At this time, the write address counter of FIFO (A) is incremented.
When WEA is "H", this IC disable to write data into FIFO (A) and
the write address counter of FIFO (A) is not incremented.
When write reset input WRESA is "L", the write address counter of
FIFO (A) is initialized.
When read enable input REA is "L", the contents of FIFO (A) are
outputted to data output QA<3:0> in synchronization with the rising of
clock input CKA.
At this time, the read address counter of FIFO (A) is incremented.
When REA is "H", this IC disable to read data from FIFO (A) and
the read address counter of FIFO (A) is not incremented.
Also QA<3:0> become high impedance state.
When read reset input RRESA is "L", the read address counter of
FIFO (A) is initialized.
2
2
2
2
2
8
8
1
2
1
9
9
They are clock inputs.
They are write enable control inputs.
When they are "L", a write enable status is
provided.
They are reset inputs to initialize a write
address counter of internal FIFO.
When they are "L", a write reset status is
provided.
They are read enable control inputs.
When they are "L", a read enable status is
provided.
They are reset inputs to initialize a read
address counter of internal FIFO.
When they are "L", a read reset status is
provided.
They are data input bus.
They are data output bus.
This is a pin for setting operation mode.
MODE should be fixed at "L".
They are pins for test.
TEST<2:1> should be fixed at "L".
This is a power on reset input.
They are 3.3 V power supply pins.
They are ground pins.
Function