r8a66120ffa Renesas Electronics Corporation., r8a66120ffa Datasheet - Page 11

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r8a66120ffa

Manufacturer Part Number
r8a66120ffa
Description
4m-bit X 2 Multiple Field Memory
Manufacturer
Renesas Electronics Corporation.
Datasheet
Variable Length Delay bits
REJ03F0161-0170 Rev.1.70 May.16.2008
R8A66120FFA
The 1-line length (cycle number) of R8A66120FFA is 1,048,576-cycle.
page 11 of 14
1-line Delay
In read cycles, an output data is read out at the (first) rising edge of CK (i.e. the start of the cycle ) .
In write cycles, an input data is written at the (second) rising edge of CK (i.e. the end of the cycle ) .
So 1-line delay can be made easily according to the control method of the following figure.
N-bit Delay 1
(Reset at cycles corresponding to delay length)
WRES
WRES
RRES
RRES
CK
Qn
CK
Dn
Qn
Dn
Note: Take care of the restriction to a interval between a write cycle and a read cycle (ref. page10).
Reset cycle
Reset
cycle
0 cycle
0 cycle
(0)
(0)
1 cycle
1 cycle
(1)
(1)
2 cycle
2 cycle
1048576 cycle
(2)
Delay length n
(2)
(1048573)
(n-2)
n-1 cycle
1048574
cycle
(1048574)
(n-1)
Reset cycle
1048575
cycle
(1048575)
1048576 (0’)
cycle
0 cycle
0’ cycle
0 cycle
1048576
WE, RE=“L”
(0)
WE, RE=“L”
(0’)
(0’)
(0)
1’ cycle
1 cycle
1048577 (1’)
1 cycle
cycle
in
(1’)
(1)
256
(1’)
(1)
1048578 (2’)
2’ cycle
2 cycle
cycle
2 cycle
(2’)
(2)
・・・Write side
・・・Read side
(2’)
(2)
・・・Write side
・・・Read side

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