pcd3312cp NXP Semiconductors, pcd3312cp Datasheet - Page 14

• Manufacturer Part Number: pcd3312cp
• Description: Dtmf/modem/musical-tone Generators
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 6 Explanation of time symbols used in Fig.11
8.5.2
Masters generate a bus clock with a maximum frequency of 2 kHz; a minimum LOW period of 105 s and a minimum
HIGH period of 365 s. The mark-to-space ratio is 1 : 3 LOW-to-HIGH. Detailed timing is shown in Fig.13, where the two
signal levels are LOW = V
mode.The time symbols are explained in Table 7.
1996 Nov 21
f
t
t
t
t
t
t
t
t
t
t
t
SYMBOL
SCL
SW
BUF
SU;STA
HD;STA
LOW
HIGH
r
f
SU;DAT
HD;DAT
SU;STO
handbook, full pagewidth
DTMF/modem/musical-tone generators
Clock LOW minimum = 4.7 s; clock HIGH minimum = 4 s.
The dashed line is the acknowledgment of the receiver.
Mark-to-space ratio = 1 : 1 (LOW-to-HIGH).
Maximum number of bytes is unrestricted.
Premature termination of transfer is allowed by generation of STOP condition.
Acknowledge clock bit must be provided by master.
L
OW
SCL clock frequency
tolerable pulse spike width
bus free time
set-up time repeated START
hold time START condition
SCL LOW time
SCL HIGH time
rise time SDA and SCL
fall time SDA and SCL
data set-up time
data hold time
set-up time STOP condition
-
SDA
SCL
SPEED MODE
CONDITION
START
PARAMETER
IL
ADDRESS R/W
and HIGH = V
1 - 7
Fig.12 Complete data transfer in standard mode.
8
IH
ACK
, see Chapter 11. Figure 14 shows a complete data transfer in low-speed
9
The time that the bus is free (SDA is HIGH)
before a new transmission is initiated by SDA
going LOW.
Only valid for repeated start code.
The time between SDA going LOW and the first
valid negative-going transition of SCL.
The LOW period of the SCL clock.
The HIGH period of the SCL clock.
1 - 7
DATA
14
8
REMARKS
ACK
9
CONDITION
START
PCD3311C; PCD3312C
ADDRESS
1 - 7
R/W
8
0
4.7
4.7
4.0
4.7
4.0
250
0
4.0
MIN.
ACK
Product specification
9
100
100
1.0
0.3
MAX.
STOP
MBC765
kHz
ns
ns
ns
UNIT
s
s
s
s
s
s
s
s