cym1831 Cypress Semiconductor Corporation., cym1831 Datasheet
cym1831
Manufacturer Part Number
cym1831
Description
64k X 32 Static Ram Module Semiconductor
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CYM1831.pdf
(8 pages)
31
Features
Functional Description
The CYM1831 is a high-performance 2-Mbit static RAM mod-
ule organized as 64K words by 32 bits. This module is con-
structed from eight 64K x 4 SRAMs in SOJ packages mounted
Cypress Semiconductor Corporation
Document #: 38-05270 Rev. **
• High-density 2-Mbit SRAM module
• 32-bit standard footprint supports densities from 16K
• High-speed CMOS SRAMs
• Low active power
• SMD technology
• TTL-compatible inputs and outputs
• Low profile
• Small PCB footprint
Logic Block Diagram
x 32 through 1M x 32
— Access time of 15 ns
— 5.3W (max.)
— Max. height of 0.50 in.
— 1.2 sq. in.
A
0
–A
CS
CS
CS
CS
WE
OE
15
1
2
3
4
16
64K x 4
64K x 4
64K x 4
64K x 4
SRAM
SRAM
SRAM
SRAM
4
4
4
4
I/O
I/O
I/O
I/O
•
0
8
16
24
– I/O
– I/O
– I/O
– I/O
3901 North First Street
3
11
19
27
64K x 4
64K x 4
64K x 4
64K x 4
PD
PD
SRAM
SRAM
SRAM
SRAM
0
1
- OPEN
- GND
on an epoxy laminate board with pins. Four chip selects (CS
CS
bytes. Reading or writing can be executed on individual bytes
or any combination of multiple bytes through proper use of
selects.
Writing to each byte is accomplished when the appropriate
Chip Selects (CS
LOW. Data on the input/output pins (I/O
memory location specified on the address pins (A
A
Reading the device is accomplished by taking the Chip Selects
(CS
(WE) remains HIGH. Under these conditions the contents of
the memory location specified on the address pins will appear
on the data input/output pins (I/O
The data input/output pins stay in the high-impedance state
when Write Enable (WE) is LOW or the appropriate chip se-
lects are HIGH.
Two pins (PD
density in applications where alternate versions of the
JEDEC-standard modules can be interchanged.
15
2
).
N
, CS
64K x 32 Static RAM Module
) LOW and Output Enable (OE) LOW while Write Enable
4
4
4
4
•
3
I/O
I/O
I/O
I/O
, and CS
San Jose
4
12
20
28
– I/O
0
Pin Configuration
– I/O
– I/O
– I/O
and PD
7
N
4
15
23
31
) are used to independently enable the four
) and Write Enable (WE) inputs are both
1
) are used to identify module memory
•
CA 95134
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
X
CS
CS
PD
I/O
I/O
I/O
I/O
V
I/O
I/O
I/O
I/O
NC
WE
A
A
A
A
A
).
CC
A
A
A
14
16
17
18
19
10
11
12
13
20
21
22
23
0
0
1
2
3
7
8
9
4
5
6
7
1
3
Revised March 15, 2002
ZIP/SIMM
Top View
X
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
) is written into the
•
CYM1831
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
1
3
5
7
9
408-943-2600
GND
PD
I/O
I/O
I/O
I/O
A
A
A
I/O
I/O
I/O
I/O
GND
A
CS
CS
NC
OE
I/O
I/O
I/O
I/O
A
A
A
V
A
I/O
I/O
I/O
I/O
0
CC
0
1
2
15
3
4
5
6
through
1
8
9
10
11
12
13
14
15
2
4
24
25
26
27
28
29
30
31
1
,
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