lis3dsh STMicroelectronics, lis3dsh Datasheet - Page 24

• Manufacturer Part Number: lis3dsh
• Description: Mems Digital Output Motion Sensor Ultra Low-power High Performance Three-axis “nano” Accelerometer
• Manufacturer: STMicroelectronics

Digital interfaces
Table 15.
6.2
24/53
Master ST
Slave
Table 13.
Table 14.
Transfer when master is receiving (reading) multiple bytes of data from slave
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW, to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In the presented communication format, MAK is Master acknowledge and NMAK is No
Master Acknowledge.
SPI bus interface
The LIS3DSH SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
SAD+W
Master
Master
Slave
Slave
ST
SAK
ST
Transfer when master is writing multiple bytes to slave:
Transfer when master is receiving (reading) one byte of data from slave:
SAD + W
SUB
SAD + W
SAK
SAK
SR SAD+R
SAK
Doc ID 022405 Rev 1
SUB
SUB
SAK
SAK
SAK
SR
DATA
SAD + R
DATA
MAK
DATA
SAK
SAK
MAK
DATA
DATA
DATA
NMAK
SAK
NMAK
LIS3DSH
SP
SP
SP