lis3l02ds STMicroelectronics, lis3l02ds Datasheet - Page 7

• Manufacturer Part Number: lis3l02ds
• Description: Three Axis 2g-6g Linear Accelerometer
• Manufacturer: STMicroelectronics

2
The registes embedded inside the LIS3L02DS may be accessed through both the 2C and SPI serial in-
terfaces. The latter may be SW configured to operate either in SPI mode or in 3-wire interface mode.
The serial interfaces are mapped onto the same pads. To select/exploit the I2C interface, CS line must be
tied high (i.e connected to Vdd).
Table 1. Serial Interface Pin Description
2.1 I2C Serial Interface
The LIS3L02DS I2C is a bus slave. The I2C is employed to write the data into the registers whose content
can also be read back.
The relevant I
Table 2. Serial Interface Pin Description
There are two signals associated with the I
(SDA). The latter is a bidirectional line used for sending and receiving the data to/form the interface. Both
the lines are connected to Vdd through a pull-up resistor embedded inside the LIS3L02DS. When the bus
is free both the lines are high.
2.1.1 I
The transaction on the bus is started through a START signal. A START condition is defined as a HIGH
to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the
Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the
address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the
slave or transmitting data to the slave. When an address is sent, each device in the system compares the
first seven bits after a start condition with it’s address. If they match, the device considers itself addressed
by the Master. The address can be made up of a programmable part and a fixed part, thus allowing more
than one device of the same type to be connected to the I
The Slave ADdress (SAD) associated to the LIS3L02DS is 0011101.
Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the ac-
CS
SCL/SPC
SDA/SDI/SDO
SDO
Transmitter
Receiver
Master
Slave
DIGITAL INTERFACES
PIN Name
2
C Operation
Term
2
C terminology is given in the table below
SPI enable
I2C/SPI mode selection (1: I2C mode; 0: SPI enabled)
I2C Serial Clock (SCL)
SPI Serial Port Slock (SPC)
I2C Serial Data (SDA)
SPI Serial Data Input (SDI)
3-wire Interface Serial Data Output (SDO)
SPI Serial Data Output (SDO)
The device which sends data to the bus
The device which receives data from the bus
The device which initiates a transfer, generates clock signals and terminates a transfer
The device addressed by the master
2
C bus: the Serial Clock Line (SCL) and the Serial DAta liine
PIN Description
Description
2
C bus.
LIS3L02DS
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