pth12040 Astec Powe, pth12040 Datasheet - Page 5

• Manufacturer Part Number: pth12040
• Description: Pth12040 12vin Single
• Manufacturer: Astec Powe

3.1 Mechanical Outline Drawings
3. Mechanical Information
Tolerances (unless otherwise specified)
Tolerances (unless otherwise specified)
Figure 1 - Plated Through-Hole Mechanical Drawing - Suffix H
Dimensions in Inches (mm)
Dimensions in Inches (mm)
(23.49)
0.925
2 Places ±0.030 (±0.76)
3 Places ±0.010 (±0.25)
(23.49)
2 Places ±0.030 (±0.76)
3 Places ±0.010 (±0.25)
0.925
0.060 (1.52)
(1.52)
Figure 2 - Surface Mount Mechanical Drawing - Suffix S
0.125 (3.17)
6 Places
0.060
0.060 (1.52)
6 Places
(1.52)
0.125 (3.17)
0.060
(3.17)
3 Places
0.125
(3.17)
3 Places
0.125
17
17
18
19
20
20
1
18
19
16
1
16
(9.52)
(9.52)
0.375
0.375
0.375
(9.52)
(9.52)
0.375
15
2
2 Places
15
(6.35)
2
2 Places
0.250
(6.35)
14
0.250
14
1.875 (47.62)
13
2.045 (51.94)
3
1.875 (47.62)
2.045 (51.94)
13
3
TOP VIEW
TOP VIEW
(9.52)
(9.52)
0.375
0.375
(9.52)
0.375
0.375
(9.52)
12
4
12
4
11
File Name: an_pth12040.pdf Rev (02): 21 Dec 2005
11
10
5
10
5
(9.52)
0.375
(9.52)
0.375
(9.52)
0.375
(9.52)
0.375
6
9
6
9
8
7
7
8
0.125 (3.17)
0.125 (3.17)
1.045
(26.54)
1.045
(26.54)
(3.55)
0.140
0.370 (9.40)
MAX.
SIDE VIEW
SIDE VIEW
After solder reflow
on customer board
0.357 (9.07)
Solder Ball
20 Places
Host Board
ø
MAX.
Bottom side
Clearance
Lowest
Component
0.010 MIN.
(0.25)
0.040 (1.02)
ø0.040 (1.02)
20 Places
3.2 Pin-out Table
3.3 Pin Description
3.3.1 Ground
This is the common ground connection for the V
connections. It is also the 0VDC reference for the control inputs.
3.3.2 V
The positive input voltage power node to the module, which is
referenced to common GND.
3.3.3 Inhibit
The Inhibit pin is an open-collector/drain negative logic input that is
referenced to GND. Applying a low level ground signal to this input
disables the module’s output and turns off the output voltage. When
the Inhibit control is active, the input current drawn by the regulator
is significantly reduced. If the Inhibit pin is left open-circuit, the
module will produce an output whenever a valid input source is
applied.
3.3.4 UVLO Programming
Connecting a resistor from this pin to signal ground allows the ‘on’
threshold of the input undervoltage lockout (UVLO) to be adjusted
higher than the default value. The Hysteresis can also be
independently reduced by connecting a second resistor from this pin
to V
3.3.5 V
The regulated positive power output with respect to the GND node.
Application Note 193
in
www.artesyn.com
. See Section 7.2.
in
out
PIN NO.
Table 3 - Pin Connections
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
PIN CONNECTIONS
UVLO Programming
Margin Down
FUNCTION
Margin Up
+Vsense
-Vsense
Ground
Ground
Ground
Ground
Ground
Ground
Inhibit
Adjust
Track
Vout
Vout
Vout
Vin
Vin
Vin
in
and V
out
power
5