pth12040 Astec Powe, pth12040 Datasheet - Page 11

• Manufacturer Part Number: pth12040
• Description: Pth12040 12vin Single
• Manufacturer: Astec Powe

7.4 Margin Up/Down Controls
The PTHxx060W, PTHxx010W, PTHxx020W, PTHxx030W and
PTHxx040W module series incorporate Margin Up and Margin Down
control inputs. These controls allow the output voltage set point to
be momentarily adjusted
provides a convenient method for dynamically testing the operation
of the load circuit over its power supply margin or range. The ±5%
change is applied to the adjusted output voltage as set by the
external resistor, R set at the V o Adjust pin.
The 5% adjustment is made by driving the appropriate margin
control input directly to the GND terminal
drain device, such as a MOSFET or p-channel JFET is recommended
for this purpose. Adjustments of less than 5% can also be
accommodated by adding series resistors to the control inputs (See
Figure 11). The value of the resistor can be selected from Table 6 or
calculated using the following formula.
7.4.1 Up/Down Adjust Resistance Calculation
To reduce the margin adjustment to something less than 5%, series
resistors are required (See R
amount of adjustment, the resistor value calculated for R
will be the same. The formula is as follows.
Where ∆% = The desired amount of margin adjust in percent.
Notes:
1 The Margin Up and Margin Down controls were not intended to
2 The ground reference should be a direct connection to the
3 The Margin Up and Margin Dn control inputs are not compatible
HORIZ SCALE: 10 ms/Div
Figure 10 - Typical Rise in Output Voltage and Input Current
be activated simultaneously. If they are their affects on the output
voltage may not completely cancel, resulting in the possibility of a
slightly higher error in the output voltage set point.
module GND. This will produce a more accurate adjustment at
the load circuit terminals. The transistors Q1 and Q2 should be
located close to the regulator.
with devices that source voltage. This includes TTL logic. These
are analog inputs and should only be controlled with a true open-
drain device (preferably a discrete MOSFET transistor). The
device selected should have low off-state leakage current. Each
input sources 8µA when grounded, and has an open-circuit
voltage of 0.8V.
(1)
, either up or down, by a nominal 5%. This
D
and R
File Name: an_pth12040.pdf Rev (02): 21 Dec 2005
U
in Figure 15). For the same
(2)
. A low-leakage open-
Iin (2A/Div)
Q1Vds (5V/Div)
D
Vo (2V/Div)
and R
U
7.5 Remote Sense
The V
datasheet standard application). A remote sense improves the load
regulation performance of the module by allowing it to compensate
for any ‘IR’ voltage drop between itself and the load. An IR drop is
caused by the high output current flowing through the small amount
of pin and trace resistance. Use of the remote sense is optional. If
not used, the Vout Sense pin can be left open-circuit. An internal
low-value resistor (15Ω or less) is connected between the V
and V
With the sense pin connected, the difference between the voltage
measured directly between the V
measured from V
compensated by the regulator. This should be limited to a maximum
of 0.3V.
Note: The remote sense feature is not designed to compensate for
the forward drop of non-linear or frequency dependent components
that may be placed in series with the converter output. Examples
include OR-ing diodes, filter inductors, ferrite beads, and fuses.
When these components are enclosed by the remote sense
connection they are effectively placed inside the regulation control
loop, which can adversely affect the stability of the regulator.
Application Note 193
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o
out
Figure 11 - Margin Up/Down Application Schematic
Sense pin should be connected to V
GND
, ensures that the output voltage remains in regulation.
MargUp
V
MargDown
in
Table 6 - Margin Up/Down Resistor Values
C
in
+
out
Q
Sense to GND, is the amount of IR drop being
R
% ADJUST
1
D
Q
R
2
u
5
4
3
2
1
1
2
out
and GND pins, and that
PTH05010
(Top View)
10
3
150.0kΩ
397.0kΩ
24.9kΩ
66.5kΩ
R
0.0kΩ
9
4
U
8
5
R
/R
SET
out
D
0.1W, 1%
at the load circuit (see
7
6
C
+V
0V
out
o
o
+
Sense
GND
+V
out
11
L
O
A
D