il511-3etr7 NVE Corp., il511-3etr7 Datasheet - Page 8

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il511-3etr7

Manufacturer Part Number
il511-3etr7
Description
2 Mbps Dc-correct Digital Isolators
Manufacturer
NVE Corp.
Datasheet
Notes (apply to both 3.3 V and 5 V specifications):
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If internal clock is used, devices will respond to DC states on inputs within a maximum of 9 µs. Outputs may oscillate if SYNC input slew rate
11. t
Absolute maximum ambient operating temperature means the device will not be damaged if operated under these conditions. It does not
guarantee performance.
PWD is defined as |t
t
CM
common mode input voltage that can be sustained while maintaining V
and falling common mode voltage edges.
Device is considered a two terminal device: pins on each side of the package are shorted.
Dynamic power consumption is calculated per channel and is supplied by the channel’s input side power supply.
Minimum pulse width is the minimum value at which specified PWD is guaranteed.
The relevant test and measurement methods are given in the Electromagnetic Compatibility section on p. 9.
External magnetic field immunity is improved by this factor if the field direction is “end-to-end” rather than to “pin-to-pin” (see diagram on p. 9).
is less than 1 V/ms.
off
PSK
is the maximum time for the internal clock to shut down.
is the magnitude of the worst-case difference in t
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
PHL
− t
PLH
|. %PWD is equal to PWD divided by pulse width.
PHL
and/or t
IL510/IL511/IL514/IL515/IL516
PLH
between devices at 25°C.
8
O
< 0.8 V. The common mode voltage slew rates apply to both rising
O
> 0.8 V
DD
2
. CM
L
is the maximum

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