ne56610 NXP Semiconductors, ne56610 Datasheet - Page 9

• Manufacturer Part Number: ne56610
• Description: Family Of Devices Designed To Generate A Reset Signal For A Variety Of Microprocessor And Logic Systems
• Manufacturer: NXP Semiconductors

Philips Semiconductors
TIMING DIAGRAM
The Timing Diagram shown in Figure 17 depicts the operation of the
device. Letters indicate events on the TIME axis.
A: At start-up, event ‘A’, the V
to rise. The reset voltage initially starts to rise but then abruptly
returns to a LOW voltage state. This is due to V
(approximately 0.8 V) which activates the internal bias circuitry
asserting a RESET state at V
B: At event ‘B’, the fixed internal delay time (t
is caused and coincident to V
At this level the device is in full operation. The output remains in a
low voltage state as V
C: At event ‘C’, V
(V
instant the device releases the hold on V
goes to a high state.
In a microprocessor-based system these events remove the reset
from the microprocessor, allowing the microprocessor to be fully
functional.
D-E: At event ‘D’, V
continues to fall until the undervoltage threshold (V
‘E’. This causes the device to generate a reset signal.
2003 Oct 31
SL
System reset
) and the fixed internal delay time (t
RESET
V
V
OUT
M/R
CC
V
SS
= V
V
V
V
V
0
CC
SH
SL
CC
is above the undervoltage detection threshold
A
CC
begins to ramp down and V
rises above V
OUT
CC
CC
B
rising to the threshold level of V
.
and V
t
DLH
V
RES
SH
OUT
DLH
OUT
. This is normal.
C
) has elapsed. At this
(RESET) voltages begin
and V
DLH
CC
) is initiated. This
SL
reaching a level
OUT
OUT
) is reached at
(RESET)
follows. V
D
Figure 17. Timing diagram.
E
SH
F
CC
.
t
DLH
9
G
E-F: Between ‘E’ and ‘F’, V
F: At event ‘F’, V
the t
G: At event ‘G’, V
voltage and the t
point the device releases the hold on V
HIGH state.
H-K: At event ‘H’, V
voltage state) has been applied to the M/R pin. This forces the
output into a reset (LOW voltage state). Removal of the manual
reset voltage, at ‘J’, from the M/R pin initiates the fixed internal delay
time, and at ‘K’, the internal delay time has elapsed and V
to a HIGH voltage state.
L: At event ‘L’, V
and the output goes into low voltage reset condition.
M: At event ‘M’, the V
normal internal circuit bias is no longer able to maintain the device
and V
V
decays even further, V
OUT
DLH
OUT
may exhibit a slight rise to something less than 0.8 V. As V
H
fixed internal delay time is initiated.
reset assertion is no longer be guaranteed. As a result,
J
DLH
CC
CC
t
DLH
CC
CC
sags to the V
reaches the upper threshold (V
fixed internal delay time has elapsed. At this
is above the V
CC
OUT
is normal, but a manual reset voltage (HIGH
K
voltage has deteriorated to a level where
reset also decays to zero.
CC
recovers and starts to rise.
NE56610/11/12-XX
SL
SL
undervoltage threshold level
TIME
OUT
undervoltage detection
L
and V
M
V
OUT
S
SH
SL01381
goes to a
). Once again,
Product data
OUT
goes
CC