km432s2030c Samsung Semiconductor, Inc., km432s2030c Datasheet - Page 38

• Manufacturer Part Number: km432s2030c
• Description: 2m X 32 Sdram 512k X 32bit X 4 Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

CLOCK
KM432S2030C
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
A
ADDR
10
DQM
CKE
RAS
CAS
BA
BA
/AP
WE
DQ
CS
0
1
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
0
Row Active
(A-Bank)
RAa
RAa
1
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC
3. Burst stop is valid at every burst length.
4. For -6/7/8/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency.
DQM at write interrupted by precharge command is needed to prevent invalid write.
parameter of t
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
2
3
(A-Bank)
Write
CAa
DAa0 DAa1 DAa2 DAa3 DAa4
RDL.
4
5
6
7
8
Burst Stop
9
tBDL
HIGH
10
(A-Bank)
Write
DAb0 DAb1 DAb2 DAb3 DAb4
CAb
11
12
13
14
15
DAb5
REV. 1.1 Mar. '99
CMOS SDRAM
16
*Note 2,4
17
Precharge
(A-Bank)
18
tRDL
: Don't care
19