km432s2030c Samsung Semiconductor, Inc., km432s2030c Datasheet - Page 20

• Manufacturer Part Number: km432s2030c
• Description: 2m X 32 Sdram 512k X 32bit X 4 Banks Synchronous Dram Lvttl
• Manufacturer: Samsung Semiconductor, Inc.

KM432S2030C
10. Clock Suspend Exit & Power Down Exit
11. Auto Refresh & Self Refresh
*Note : 1. Active power down : one or more banks active state.
1) Clock Suspend (=Active Power Down) Exit
1) Auto Refresh & Self Refresh
2) Self Refresh
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
Internal
No precharge commands are required after auto refresh command.
During t
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of t
Before/After self refresh mode, burst auto refresh cycle (4096 cycles) is recommended.
CMD
CMD
CMD
CLK
CKE
CKE
CKE
CLK
CLK
CLK
RFC
from auto refresh command, any other command can not be accepted.
Note 6
Note 1
PRE
PRE
RFC
Note 4
Note 4
from self refresh exit command, any other command can not be accepted.
tRP
tRP
Note 3
tSS
AR
SR
RD
tRFC
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
- 20
2) Power Down (=Precharge Power Down) Exit
Internal
¡ó
CMD
CMD
CKE
CLK
CLK
tRFC
Note 5
Note 2
CMD
NOP
REV. 1.1 Mar. '99
tSS
CMOS SDRAM
ACT