npe405h Applied Micro Circuits Corporation (AMCC), npe405h Datasheet - Page 44

• Manufacturer Part Number: npe405h
• Description: Powernp Npe405h Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

NPe405H – PowerNP NPe405H Embedded Processor
Table 6. Signal Functional Description (Sheet 2 of 9)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
3. Must pull down. See “Pull-up and Pull-down Resistors” on page 42 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Peripheral Bus Control Signals” on page 42.
44
HDLCEX Interface
HDLCMP Interface
Ethernet Interface
DS2011
[HDLCMPRxData4:7]
[HDLCMPTxData4:7]
HDLCMPTxData0:3
[HDLCMPRxClk4:7]
HDLCMPRxData0:3
[HDLCMPTxClk4:7]
[HDLCMPTxEn0:7]
HDLCMPRxClk0:3
HDLCEXRxDataA
HDLCEXRxDataB
HDLCMPTxClk0:3
HDLCEXTxDataA
HDLCEXTxDataB
[HDLCEXTxEnA]
[HDLCEXTxEnB]
HDLCEXRxClk
HDLCEXTxClk
HDLCEXRxFS
HDLCEXTxFS
Signal Name
EMC0MDClk
EMC0MDIO
PCIGnt1:5
PCIGnt1:5 output when internal arbiter is used.
Transmit Clock
Transmit Frame Synchronization
Transmit Data port A
Transmit Data port B
Receive Clock
Receive Frame Synchronization
Receive Data port A
Receive Data port B
Transmit Enable port A
Transmit Enable port B
Transmit Clock signal that controls the transmit bit rate
Transmit Clock signal that controls the transmit bit rate
Transmit Data signal
Transmit Data signal
Transmit Data Enable signal that controls when the external
buffer is tri-stated
Receive Clock signal that controls the receive bit rate
Receive Clock signal that controls the receive bit rate
Receive Data signal
Receive Data signal
Management Data Clock. The MDClk is sourced to the PHY.
Management information is transferred synchronously with
respect to this clock (MII, RMII, and SMII).
Management Data Input/Output is a bidirectional signal
between the Ethernet controller and the PHY. It is used to
transfer control and status information (MII, RMII, and SMII).
Description
Revision 1.02 – November 16, 2007
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
3.3V PCI
Type
Data Sheet
AMCC Proprietary
Notes
1, 4