npe405h Applied Micro Circuits Corporation (AMCC), npe405h Datasheet - Page 10

• Manufacturer Part Number: npe405h
• Description: Powernp Npe405h Embedded Processor
• Manufacturer: Applied Micro Circuits Corporation (AMCC)

NPe405H – PowerNP NPe405H Embedded Processor
SDRAM MEMORY CONTROLLER
The NPe405H Memory Controller provides a low latency access path to SDRAM memory. The memory controller
supports four logical banks. Up to 256MB per bank are supported, for a maximum of 1GB total. Memory access
and refresh timing, address and bank sizes, and memory addressing modes are programmable.
Features include:
EXTERNAL BUS CONTROLLER (EBC)
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DS2011
11x8 to 13x11 row-column address modes (2- and 4-bank devices supported)
Memory bus operates at same frequency as PLB
32-bit memory interface support
Programmable address range for each bank of memory
- 4GB address space
Industry standard 168-pin DIMMS are supported (some configurations)
200 MHz NPe405H supports up to 100 MHz memory with PC100 support
266 MHz NPe405H supports up to 133 MHz memory with PC133 support
4MB to 256MB per bank
Programmable timing
Auto refresh
Page Mode Accesses with up to 4 open pages
Power Management (self-refresh)
Error Checking and Correction (ECC) support
- Standard single error correct, double error detect coverage
- Aligned nibble error detect
- Address error logging
Supports eight ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported
Up to 66.66MHz operation
Burst and non-burst devices
8-, 16-, 32-bit byte-addressable data bus width support
Latch data on Ready, Synchronous or Asynchronous
Programmable 2K clock-cycle time-out counter with disable for Ready
Programmable access timing per device
- 0–255 wait states for non-bursting devices
- 0 –31 Burst Wait States for first access and up to 7 Wait States for subsequent accesses
- Programmable chip select assertion/negation relative to driving address bus
- Programmable output and write-enable assertion/negation relative to assertion of chip select
Programmable address mapping
Peripheral device wait via “Ready”
External master interface
- Write posting from external master
- Read prefetching on PLB for external master reads
- Bursting capable from external master
- Allows external master access to all non-EBC PLB slaves
- External master can control EBC slaves for own access and control
Revision 1.02 – November 16, 2007
Data Sheet
AMCC Proprietary