am53c94 Advanced Micro Devices, am53c94 Datasheet - Page 34

• Manufacturer Part Number: am53c94
• Description: High Performance Scsi Controller
• Manufacturer: Advanced Micro Devices

COMMAND DESCRIPTION
Initiator Commands
Initiator commands are executed by the device when it
is in the initiator mode. If the device is not in the initiator
mode and an initiator command is received the device
will ignore the command, generate an illegal command
interrupt and clear the Command Register (CMDREG)
03H.
Information Transfer Command
(Command Code 10H/90H)
The Information Transfer command is used to transfer
information bytes over the SCSI bus. This command
may be issued during any SCSI Information Transfer
phase. Information transfer for synchronous data must
use the DMA mode.
The device will continue to transfer information until it is
terminated by any one of the following conditions:
During synchronous data transfers the target may send
up to the maximum synchronous threshold number of
REQ pulses to the initiator. If it is the Synchronous Data-
In phase then the target sends the data and the REQ
pulses. These bytes are stored by the initiator in the
FIFO as they are received.
Information Transfer Command when issued during the
following SCSI phases and terminating in synchronous
data phases, is handled as described below:
34
The target changes the SCSI bus phase before the
expected number of bytes are transferred. The
device clears the Command Register (CMDREG)
03H, and generates a service interrupt when the
target asserts REQ.
Transfer is successfully complete. If the phase is
Message Out, the device deasserts ATN before
asserting ACK for the last byte of the message.
When the target asserts REQ, a service interrupt is
generated.
In the Message In phase when the device receives
the last byte. The device keeps the ACK signal
asserted and generates a Successful Operation
interrupt.
Message In/Status Phase – When a phase change
to Synchronous Data-In or Synchronous Data-Out is
detected by the device, the Command Register
(CMDREG) 03H is cleared and the DMA interface is
disabled to disallow any transfer of data phase bytes.
If the phase change is to Synchronous Data-In and
bad parity is detected on the data bytes coming in, it
is
(STATREG) 04H will report the status of the
command just completed. The parity error flag and
the ATN signal will be asserted when the Transfer
Information command begins execution.
AMD
not
reported
since
the
Status
P R E L I M I N A R Y
Register
Am53C94/Am53C96
Initiator Command Complete Steps
(Command Code 11H/91H)
The Initiator Command Complete Steps command is
normally issued when the SCSI bus is in the Status In
phase. One Status byte followed by one Message byte
is transferred if this command completes normally. After
receiving the message byte the device will keep the
ACK signal asserted to allow the initiator to examine the
message and assert the ATN signal if it is unacceptable.
The command terminates early if the target does not
switch to the Message In phase or if the target discon-
nects from the SCSI bus.
Message Accepted Command
(Command Code 12H)
The Message Accepted Command is used to release
the ACK signal. This command is normally used to com-
plete a Message In handshake. Upon execution of this
command the device generates a service request inter-
rupt after REQ is asserted by the target.
Message Out/Command Phase – When a phase
change to Synchronous Data-In or Synchronous
Data-Out is detected by the device, the Command
Register (CMDREG) 03H is cleared and the DMA
interface is disabled to allow any transfer of data
phase bytes. If the phase change is to Synchronous
Data-In and bad parity is detected on the data bytes
coming in, it is not reported since the Status Register
(STATREG) 04H will report the status of the
command just completed. The parity error flag and
the ATN signal will be asserted when the Transfer
Information command begins execution. The FIFO
Register29 (FFREG) 02H will be latched and will
remain in that condition until the next command
begins execution. The value in the FFREG indicates
the number of bytes in the FIFO when the phase
changed to Synchronous Data-In. These bytes are
cleared from the FIFO, which now contains only the
incoming data bytes.
In the Synchronous Data-Out phase, the threshold
counter is incremented as REQ pulses are received.
The transfer is completed when the FIFO is empty
and the Current Transfer Count Register (CTCREG)
00H–01H is zero. The threshold counter will not be
zero.
In the Synchronous Data-In phase, the Current
Transfer Count Register
mented as bytes are read from the FIFO rather than
being decremented when the bytes are being written
to the FIFO. The transfer is completed when Current
Transfer Count Register (CTCREG) is zero but the
FIFO may not be empty.
(CTCREG) is decre-