saa5254 NXP Semiconductors, saa5254 Datasheet - Page 17

• Manufacturer Part Number: saa5254
• Description: Integrated Vip And Teletext Decoder Ivt1.1x
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Notes to Table 7
1. The dash ( ) indicates these bits are inactive and must be written to logic 0 for future compatibility.
2. All bits in Registers R0 to R13 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6
3. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white
4. TB must be set to logic 0 for normal operation.
5. The I
Table 8 Register description
1996 Nov 07
R0 AVANCED CONTROL - auto-increments to Register 1
R11/R11B SELECT
DISABLE ODD/EVEN
DISPLAY STATUS ROW
DISABLE HDR ROLL
AUTO ODD/EVEN
FREE RUN PLL
X/24 POS
R1 MODE - auto-increments to Register 2
T0, T1
TCS ON
DEW/FULL FIELD
ACQ ON/OFF
7 + P/8-BIT
DISABLE PKT 26
VCS TO SCS
R2 PAGE REQUEST ADDRESS - auto-increments to Register 3
START COLUMN SC0 to SC2
TB
R3 PAGE REQUEST DATA - does not auto-increment (see Table 9)
R5 NORMAL DISPLAY CONTROL - auto-increments to Register 6
R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto-increments to Register 7; note 1
PON
TEXT
COR
BKGND
Integrated VIP and teletext decoder
(IVT1.1X)
which are set to logic 1.
(00000111) as the acquisition circuit is enabled but all pages are on hold.
REGISTER BIT D0 TO D7
2
C-bus slave address is 00110001.
Selects reading of R11 if LOW or if HIGH R11B.
Forces ODD/EVEN output LOW when logic 1.
When SET = 1 and R1D6 = 1 open (8-bit mode) then all the text display is blanked
out apart from the status row, this allows the page memory to be used for
non-textural data, such as in the German TOP system.
Disables green rolling header and time.
When SET forces ODD/EVEN LOW if any TV picture displayed, if DISABLE
ODD/EVEN = 0
Will force the display PLL to free run in all conditions.
Automatic display of FASTEXT prompt row when logic 1.
Interlace/non-interlace 312/313 line control (see Table 10).
Text composite sync or direct sync select (see Table 10 for FFB mode selection).
Field-flyback or full-channel mode.
Acquisition circuits turned off when logic 1.
7 bits with parity checking or 8-bit mode.
Disable automatic processing of packet 26.
When logic 1 enables display of messages with 60 Hz input signal.
Point to start column for page request data (see Table 9).
Must be logic 0 for normal operation.
Picture on.
Text on.
Contrast reduction on.
Background colour on.
17
FUNCTION
Preliminary specification
SAA5254