saa5281 NXP Semiconductors, saa5281 Datasheet - Page 24

• Manufacturer Part Number: saa5281
• Description: Integrated Video Input Processor And Teletext Decoder Ivt1.8
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Note
1. These functions have IN and OUT referring to inside and outside the boxing function respectively.
Table 9 ODD/EVEN selection
Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option
Notes
1. X = don't care.
2. Reverts to interlaced mode if a newsflash or subtitle is being displayed.
1996 Nov 04
R13 ADVANCED CONTROL 2B - does not auto-increment
AUTO DISPLAY PKT X/24
DISABLE PKT X/26
HAM CHECK 24 : 18
POINTS ENABLE
VPS ENABLE
MESHING ENABLE
CURSOR FREEZE/
DEVICE IDENT
ENHANC MODE
FFB MODE
Integrated Video input processor and
Teletext decoder (IVT1.8*)
ODD/EVEN
REGISTER BIT D0 TO D7
TCS ON
AUTO
X
X
X
0
0
1
1
0
1
(1)
ODD/EVEN
T1
DISABLE
0
0
1
1
1
0
1
1
1
T0
0
1
0
1
1
Status row will show the contents of the row of the extension memory (packet 24)
when logic 1.
Output taken from processing engine written to the display memory when logic 0.
Operates independent of the acquisition.
When logic 1 all packet 26 data is stored in extension memory unchecked.
Enable for acquisition pointers when logic 1.
VPS acquisition enabled when logic 1.
Enables meshing display function in box mode.
When logic 1, cursor position not updated even if active row and column change.
This bit will also cause R3 and R4 of the ROM code in Register R11B to be set
HIGH. This allows software to identify the device as an IVT1.8*. An internal ‘1.8
mode’ flag is also set, which enables the operation of R0D4, R4D4 and the subtitle
bit in R3.
When logic 1, extension packet data is mapped into the last chapter. Only packet
24, 27/0 and 8/30 are stored. Chapters 0 to 6 can then be used for page storage. If
extension packets are not enabled, 8 pages are stored as normal, but X/26 engine
is enabled.
ODD/EVEN output continuous
ODD/EVEN statically LOW
ODD/EVEN active only when no TV picture displayed
DV output to indicate reception of error-free 8/30/format 2 packet or VPS line
interlaced 312.5/312.5 lines
non-interlaced 312/313 lines (note 2)
non-interlaced 312/313 lines (note 2)
SCS (scan composite sync) mode: FFB leading edge in first broad pulse of field
SCS (scan composite sync) mode: FFB leading edge in second broad pulse of field
24
FUNCTION
RESULT
RESULT
Preliminary specification
SAA5281