mt8jtf12864az Micron Semiconductor Products, mt8jtf12864az Datasheet - Page 4
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mt8jtf12864az
Manufacturer Part Number
mt8jtf12864az
Description
1gb, 2gb X64, Sr 240-pin Ddr3 Sdram Udimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT8JTF12864AZ.pdf
(14 pages)
Table 6: Pin Descriptions
PDF: 09005aef837d3ecf
JTF8C128_256x64AZ.pdf – Rev. C 9/09
RAS#, CAS#,
DQS#[7:0]
CK0#[1:0]
DQS[7:0],
DQ[63:0]
Symbol
DM[7:0]
CK[1:0],
A[14:0]
BA[2:0]
RESET#
SA[2:0]
V
V
V
ODT0
CKE0
WE#
SDA
V
DDSPD
REFDQ
S0#
SCL
REFCA
DD
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the mem-
ory array in the respective bank. A10 is sampled during a PRECHARGE command to determine
whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks
(A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also used
for BC4/BL8 identification as “BL on-the-fly” during CAS commands. The address inputs also pro-
vide the op-code during the mode register command set. A[13:0] address the 1Gb DDR3
devices. A[14:0] address the 2Gb DDR3 devices.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2,
and MR3) is loaded during the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All control, command, and address input sig-
nals are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data (DQ and DQS/DQS#) is referenced to the crossings of CK and CK#. CK1, CK1# are
terminated.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry
and clocks on the DRAM.
Data input mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled HIGH, along with the input data, during a write access. DM is sampled on both edges
of the DQS. Although the DM pins are input-only, the DM loading is designed to match that of
the DQ and DQS pins.
On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS, DQS#, and
DM. The ODT input will be ignored if disabled via the LOAD MODE command.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered.
Reset: An active LOW CMOS input referenced to V
put defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × V
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command decoder.
Presence-detect address inputs: These pins are used to configure the temperature sensor/
SPD EEPROM address range on the I
Serial clock for presence-detect: SCL is used to synchronize the communication to and from
the temperature sensor/SPD EEPROM.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the
temperature sensor/SPD EEPROM on the module on the I
Power supply: 1.5V ±0.075V.
Serial EEPROM positive power supply: +3.0V to +3.6V. The component V
connected to the module V
Reference voltage: Control, command, and address (V
Reference voltage: DQ, DM (V
1GB, 2GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
DD
.
DD/2
4
2
).
C bus.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
SS
. The RESET# input receiver is a CMOS in-
DD/2
2
DD
C bus.
).
and DC LOW ≤ 0.2 × V
©2009 Micron Technology, Inc. All rights reserved.
DDQ
and V
DD
.
DDQ
are