cym9262a Cypress Semiconductor Corporation., cym9262a Datasheet

no-image

cym9262a

Manufacturer Part Number
cym9262a
Description
64k 128k, 256k, 512k X 72 Sram Module
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
62A
Features
Functional Description
The CYM9260, CYM9261, CYM9262, and the CYM9263 are
high-performance synchronous memory modules organized
as 64K(9260), 128K(9261), 256K(9262), or 512K(9263) by 72
bits. These modules are constructed from either 128K x
18(9260,9261B,9262A) or 256K x 18 (9263) SRAMs in plastic
Cypress Semiconductor Corporation
Document #: 38-05002 Rev. **
Logic Block Diagram - CYM9260
• Operates at 66 MHz
• Uses 64K x 18, 128K x 18, or 256K x 18 high performance
• 168-position Angled DIMM from Amp p/n 179508-2
• 3.3V inputs/data outputs
CLK[0:3]
WE[7:0]
CS[0:1]
R1, R2, R3, R4 are optional resistors
R1, R2, R4 are mounted for access using ADSC
R3, R2, R4 are mounted for access using ADSP
OE[0:1]
A[15:0]
synchronous SRAMs
64Kx72
ADSP
PD
GND
1
PD
NC
0
BANK 0
R1
R3
3901 North First Street
V
R4
cc3
CS0
OE0
V
R2
cc3
WEH
WEL
ADSC
surface mount packages on an epoxy laminate board with
pins. The modules are designed to be incorporated into large
memory arrays.
The module is configured as either one or two banks, where
each bank has separate chip select and output enable con-
trols. Separate clocks are provided for every pair of SRAMs’s.
Multiple ground pins and on-board decoupling capacitors en-
sure high performance with maximum noise immunity.
All components on the cache modules are surface mounted on
a multi-layer epoxy laminate (FR-4) substrate. The contact
pins are plated with 150 micro-inches of nickel covered by 30
micro-inches of gold flash.
ADSP
OE
CS
A
15:0
BANK 0
DQ[0:15]
DQP[0:1]
128K x 72 SRAM Module
256K x 72 SRAM Module
512K x 72 SRAM Module
San Jose
64K x 72 SRAM Module
CLK
CA 95134
Revised March 27, 2002
CYM9261B
CYM9262A
CYM9260
CYM9263
408-943-2600
D[0:63]
DP[0:7]

Related parts for cym9262a

cym9262a Summary of contents

Page 1

... ADSP OE0 OE CS0 CS WEH WEL R1 ADSC BANK 0 • 3901 North First Street CYM9261B CYM9262A 64K x 72 SRAM Module 128K x 72 SRAM Module 256K x 72 SRAM Module 512K x 72 SRAM Module DQ[0:15] DQP[0:1] CLK BANK 0 • San Jose • CA 95134 Revised March 27, 2002 ...

Page 2

... Logic Block Diagram - CYM9261B/CYM9262A A[17:0] WE[0:7] ADSP OE[0:1] CS[0:1] CLK[0:3] R1, R2, R3, R4 are optional resistors R1, R2, R4 are mounted for access using ADSC R3, R2, R4 are mounted for access using ADSP GND BANK 0 128Kx72 GND GND BANK 0 & 1 256KX72 Document #: 38-05002 Rev cc3 V cc3 R2 R4 ...

Page 3

... ADSC R1 BANK 0 D[0:15] DQ[0:1] A 17:0 ADSP OE1 OE CE1 CS WEH WEL ADSC BANK 1 Synchronous Cache Module CYM9261B-66 128 128K 10.3 ns CYM9261B CYM9262A CYM9263 D[0:63] DP[0:7] CLK CLK CYM9262A-66 CYM9263-66 256 512 128K 256K 10.3 ns 10.3 ns Page ...

Page 4

... GND GND 158 74 CLK0 CLK1 159 GND 75 GND 160 75 WE6 WE7 161 77 WE4 WE5 162 78 GND GND 163 WE2 79 WE3 164 WE0 80 WE1 165 V 81 GND CC3 166 82 OE0 OE1 167 CS0 83 CS1 168 GND 84 GND CYM9261B CYM9262A CYM9263 Page ...

Page 5

... Chip Select For The Two Banks Presence Detect Output Pins Data Lines From Processor Data Parity Lines From Processor Clock Lines To The Module Address Strobe From The Processor Signal Not Connected On Module Reserved CYM9261B CYM9262A CYM9263 GND NC NC GND ...

Page 6

... CC 9262 9263 ° MHz, 9260 5.0V 9261 CC 9262 9263 ° MHz, 9260 5.0V CC 9261 9262 9262 CYM9261B CYM9262A CYM9263 Ambient Temperature V CC 0°C to +70°C 3.3V ± 5% Min. Max. Unit 2 0.3 CC –0.3 0.8 2.4 0.4 = 1/t 1000 1/t 1000 1/t 1200 ...

Page 7

... AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. EOZ Document #: 38-05002 Rev CCQ OUTPUT 3. GND INCLUDING JIG AND [2] SCOPE (b) Description [4] CYM9261B CYM9262A CYM9263 ALL INPUT PULSES 90% 90% 10% 10 CYM9260/61/62/63 66 MHz 50 MHz Min. Max. Min. Max. Unit ...

Page 8

... ADSP has no effect on ADV, WL, and HIGH. Document #: 38-05002 Rev CSS CSH ADS ADSH t t WES WEH t CDV CSS CSH ADS ADSH t WES WEH CYM9261B CYM9262A CYM9263 t CYC t DOH Page ...

Page 9

... Output (Controlled by OE) DATA OUT OE Output Timing (Controlled by CS) CLK t ADS ADSC t CSS CS DATA OUT Document #: 38-05002 Rev CSH ADSH t WES EOZ t EOZ t ADS t ADSH t CSS t CSH t CDV CYM9261B CYM9262A CYM9263 t WEH EOV t ADSH t CSH t CSOZ Page ...

Page 10

... Dual-Readout SIMM (DIMM) 168-Pin Dual-Readout SIMM (SIMM) 168-Pin Dual-Readout SIMM (DIMM) 168-Pin Dual-Readout SIMM (DIMM) 168-Pin Dual-Readout SIMM (DIMM) 168-Pin Dual-Readout SIMM (SIMM) 168-Pin Dual-Readout SIMM (DIMM) 168-Pin Dual-Readout SIMM (DIMM) CYM9261B CYM9262A CYM9263 t ADSH t WEOV Operating Description Range Sync 64K x 72 ...

Page 11

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 168-Pin Single-Sided DIMM PM43 168-Pin Dual Sided DIMM PM44 CYM9260 CYM9261B CYM9262A CYM9263 Page ...

Page 12

... Document Title: CYM9260, CYM9261B, CYM9262A, CYM9263 64K/128K/256K/512K x 72 SRAM Module Document Number: 38-05002 Issue REV. ECN NO. Date ** 114556 04/02/02 Document #: 38-05002 Rev. ** Orig. of Change Description of Change DSG Change from Spec number: 38-M-00082 to 38-05002 CYM9261B CYM9262A CYM9263 Page ...

Related keywords