m471b5273bh1 Samsung Semiconductor, Inc., m471b5273bh1 Datasheet - Page 24

• Manufacturer Part Number: m471b5273bh1
• Description: Ddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

Timing Parameters by Speed Bin (Cont.)
Command and Address Timing
DLL locking time
internal READ Command to PRECHARGE Command delay
Delay from start of internal write transaction to internal read command
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
CAS# to CAS# command delay
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
Four activate window for 1KB page size
Four activate window for 2KB page size
Command and Address setup time to CK, CK referenced to V
Command and Address hold time from CK, CK referenced to V
els
Command and Address setup time to CK, CK referenced to V
Control & Address Input pulse width for each input
Calibration Timing
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
Reset Timing
Exit Reset from CKE HIGH to a valid command
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked DLL
Exit Self Refresh to commands requiring a locked DLL
Minimum CKE low width for Self refresh entry to exit timing
Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE)
Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX)
or Reset Exit
Unbuffered SoDIMM
Parameter
Speed
IH
IH
(AC) / V
(AC) / V
IH
(AC) / V
IL
IL
(AC) levels
(AC) levels
IL
(AC) lev-
24 of 28
tDAL(min)
tIH(base)
tIS(base)
tIS(base)
tZQoper
tCKESR
tCKSRE
tCKSRX
Symbol
tXSDLL
tMPRR
AC150
tZQinitI
tZQCS
tDLLK
tWTR
tMRD
tMOD
tCCD
tRRD
tRRD
tFAW
tFAW
tRTP
tRAS
tXPR
tIPW
tWR
tXS
max(5nCK, tRFC +
max(5nCK,tRFC +
tCKE(min) + 1tCK
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,10ns)
See " Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin"
tDLLK(min)
max(5nCK,
max(5nCK,
125 + 150
10ns)
10ns)
10ns)
10ns)
MIN
max
max
max
max
max
37.5
512
125
200
780
512
256
15
50
64
4
4
1
DDR3-1066
WR + roundup (tRP / tCK(AVG))
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max(5nCK, tRFC +
max(5nCK,tRFC +
tCKE(min) + 1tCK
Rev. 1.0 December 2008
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,6ns)
tDLLK(min)
max(5nCK,
max(5nCK,
65+125
10ns)
10ns)
10ns)
10ns)
MIN
max
max
max
max
max
512
140
620
512
256
15
30
45
65
64
4
4
1
DDR3-1333
DDR3 SDRAM
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ns
ns
ps
ps
ps
ps
b,16,27
Note
e,18
b,16
b,16
22
28
23
e
e
e
e
e
e
e