m391b5273bh1 Samsung Semiconductor, Inc., m391b5273bh1 Datasheet
m391b5273bh1
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Unbuffered DIMM DDR3 SDRAM Specification 240pin Unbuffered DIMM based on 2Gb B-die 78FBGA with Lead-Free & Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL ...
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... Input/Output Functional Description ...................................................................................................................... 8 8.1 Address Mirroring Feature ................................................................................................................................ 9 8.1.1 DRAM Pin Wiring for Mirroring ................................................................................................................. 9 9.0 Functional Block Diagram: .................................................................................................................................... 10 9.1 4GB, 512Mx64 Module(Populated as 2 ranks of x8 DDR3 SDRAMs) ........................................................... 10 9.2 4GB, 512Mx72 ECC Module(Populated as 2 ranks of x8 DDR3 SDRAMs)............................................. 11 10.0 Absolute Maximum Ratings ................................................................................................................................. 12 10.1 Absolute Maximum DC Ratings..................................................................................................................... 12 10.2 DRAM Component Operating Temperature Range...................................................................................... 12 11.0 AC & ...
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Unbuffered DIMM Revision History Revision Month Year 1.0 December 2008 - First Release History DDR3 SDRAM Rev. 1.0 December 2008 ...
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... Unbuffered DIMM 1.0 DDR3 Unbuffered DIMM Ordering Information Part Number M378B5273BH1-CF8/H9/K0 M391B5273BH1-CF8/H9/K0 Note : - "##" - F8/H9/ 1066Mbps 7-7-7 & 1333Mbps 9-9-9 & 1600Mbps 11-11-11 2.0 Key Features DDR3-1066 Speed 7-7-7 tCK(min) 1.875 CAS Latency 7 tRCD(min) 13.125 tRP(min) 13.125 tRAS(min) 37.5 tRC(min) 50.625 • JEDEC standard 1.5V ± 0.075V Power Supply • ...
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Unbuffered DIMM 4.0 x64 DIMM Pin Configurations (Front side/Back side) Pin Front Pin Back 121 REFDQ 122 DQ4 SS 3 DQ0 123 DQ5 V 4 DQ1 124 125 DM0 SS 6 ...
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Unbuffered DIMM 5.0 x72 DIMM Pin Configurations (Front side/Back side) Pin Front Pin Back 121 REFDQ V 2 122 DQ4 SS 3 DQ0 123 DQ5 V 4 DQ1 124 V 5 125 DM0 SS 6 DQS0 126 ...
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... Note : 1. Raw Cards D (1Rx8 ECC) and E (2Rx8 ECC) support a thermal sensor. 2. When the SPD and the thermal sensor are placed on the module placed but R2 is not. When only the SPD is placed on the module placed but R1 is not. Temperature Sensor Characteristics ...
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... V ,V Supply DD SS these modules. DQS0-DQS8 Data strobe for input and output data. For raw cards using x16 orginized DRAMs, Pins DQ0-7 are associated with the SSTL DQS0-DQS8 LDQS and LDQS pins and Pins DQ8-15 are associated with UDQS and UDQS pins. ...
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... When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a fewrules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement that the second rank be mirrored ...
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... DQ, DM, DQS/DQS resistors: Refer to associated topology diagram. 4. Refer to section 7.1 of this document for details on SPD address mirroring D15 5. For each DRAM, a unique ZQ resistor is connected to ground. The ZQ resistor is 240 Ohm +/- D15 6. One SPD exists per module D15 D0 - D15 Rev. 1.0 December 2008 ...
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... Unbuffered DIMM 9.2 4GB, 512Mx72 ECC Module S1 S0 DQS0 DQS0 DM0 DM CS DQS DQS DQ0 I/O 0 DQ1 I DQ2 I/O 2 DQ3 I/O 3 DQ4 I/O 4 DQ5 I/O 5 DQ6 I/O 6 DQ7 I/O 7 DQS1 DQS1 DM1 DM CS DQS DQS DQ8 I/O 0 DQ9 I DQ10 I/O 2 DQ11 I/O 3 DQ12 I/O 4 DQ13 I/O 5 DQ14 I/O 6 DQ15 I/O 7 DQS2 DQS2 DM2 DM CS DQS DQS ...
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Unbuffered DIMM 10.0 Absolute Maximum Ratings 10.1 Absolute Maximum DC Ratings Symbol Parameter V Voltage on V pin relative Voltage on V pin relative to V DDQ DDQ V V Voltage on any pin relative ...
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Unbuffered DIMM 12.0 AC & DC Input Measurement Levels 12.1 AC and DC Logic Input Levels for Single-ended Signals Single Ended AC and DC input levels for Command and Address Symbol Parameter V (DC) DC input logic high IH.CA V ...
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Unbuffered DIMM 12.2 V Tolerances. REF The dc-tolerance limits and ac-noise limits for the reference voltages function of time. (V stands for V REF REF V (DC) is the linear average of V (t) over ...
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Unbuffered DIMM 12.3 AC and DC Logic Input Levels for Differential Signals 12.3.1 Differential Signals Definition V .DIFF.AC.MIN .DIFF.AC.MAX IL Figure 3 : Definition of differential ac-swing and "time above ac level" tDVAC 12.3.2 ...
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Unbuffered DIMM 12.3.3 Single-ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately ...
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Unbuffered DIMM 12.3.4 Differential Input Cross Point Voltage To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) ...
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Unbuffered DIMM 13.0 AC and DC Output Measurement Levels 13.1 Single Ended AC and DC Output Levels Single Ended AC and DC output levels Symbol Parameter V (DC) DC output high measurement level (for IV curve linearity (DC) ...
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Unbuffered DIMM 13.4 Differential Output Slew Rate With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V V (AC) for differential signals as shown in below. OHdiff Differential Output ...
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Unbuffered DIMM 14.0 IDD specification definition Symbol Description Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 ; BL: 8 IDD0 Inputs: partially toggling according to Table 32 ; Data IO: MID-LEVEL; ...
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Unbuffered DIMM Symbol Description Self-Refresh Current: Extended Temperature Range (optional) TCASE 95°C; Auto Self-Refresh (ASR): Disabled IDD6ET a) LOW; CL: see Table AL: 0; CS, Command, Address, Bank Address, Data IO: MID-LEVEL;DM:stable at ...
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... IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2Q IDD3P(fast exit) IDD3N IDD4R 1320 IDD4W 1360 IDD5B 1800 IDD6 IDD7 2160 M391B5273BH1 : 4GB(512Mx72) Module CF8 Symbol (DDR3-1066@CL=7) IDD0 IDD1 1125 IDD2P0(slow exit) IDD2P1(fast exit) IDD2N IDD2Q IDD3P(fast exit) IDD3N IDD4R 1485 IDD4W 1530 ...
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... Input capacitance (All other input-only pins) Input/output capacitance of ZQ pin M378B5273BH1 DDR3-1066 DDR3-1333 Symbol Min Max Min CIO - TBD - CCK - TBD - CI - TBD - CZQ - TBD - M391B5273BH1 DDR3-1066 DDR3-1333 Symbol Min Max Min CIO - TBD - CCK - TBD - CI - TBD - CZQ - TBD - DDR3 SDRAM ...
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Unbuffered DIMM 16.0 Electrical Characteristics and AC timing (0 °C<T ≤95 ° 1.5V ± 0.075V; V CASE DDQ 16.1 Refresh Parameters by Device Density Parameter All Bank Refresh to active/refresh cmd time Average periodic refresh interval Note : ...
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Unbuffered DIMM DDR3-1333 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = 5 ...
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Unbuffered DIMM DDR3-1600 Speed Bins Speed CL-nRCD-nRP Parameter Intermal read command to first data ACT to internal read or write delay time PRE command period ACT to ACT or REF command period ACT to PRE command period CWL = 5 ...
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Unbuffered DIMM 16.3.1 Speed Bin Table Notes Absolute Specification ( OPER DDQ DD Note : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need ...
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Unbuffered DIMM 17.0 Timing Parameters by Speed Grade Speed Parameter Clock Timing Minimum Clock Cycle Time (DLL off mode) Average Clock Period Clock Period Average high pulse width Average low pulse width Clock Period Jitter Clock Period Jitter during DLL ...
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Unbuffered DIMM Speed Parameter Command and Address Timing DLL locking time internal READ Command to PRECHARGE Command delay Delay from start of internal write transaction to internal read command WRITE recovery time Mode Register Set command cycle time Mode Register ...
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Unbuffered DIMM Speed Parameter Power Down Timing Exit Power Down with DLL on to any valid com- mand;Exit Percharge Power Down with DLL frozen to commands not requiring a locked DLL Exit Precharge Power Down with DLL frozen to com- ...
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Unbuffered DIMM 17.1 Jitter Notes Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; ...
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Unbuffered DIMM 17.2 Timing Parameter Notes 1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent ...
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... Unbuffered DIMM 18.0 Physical Dimensions : 18.1 256Mx8 based 512Mx64/x72 Module(2 Ranks) (2) 2.50 47.00 5.00 2.50 1.50±0.10 Detail A The used device is 256M x8 DDR3 SDRAM, FBGA. DDR3 SDRAM Part NO : K4B2G0846B-HC∗∗ 133.35 128.95 N/A (for x64) SPD ECC (for x72 71.00 N/A (for x64) ECC (for x72) 0.80 ± 0.05 3.80 0.2 ± 0.15 1.00 Detail B ...