hys64d32301eu-6-d Qimonda, hys64d32301eu-6-d Datasheet - Page 5

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hys64d32301eu-6-d

Manufacturer Part Number
hys64d32301eu-6-d
Description
184-pin Unbuffered Double-data-rate Memory Modules
Manufacturer
Qimonda
Datasheet
2
2.1
The pin configuration of the Unbuffered DDR SDRAM DIMM
is listed by function in
used in columns Pin and Buffer Type are explained in
Rev. 0.60, 2008-05
02142008-4Z51-SEDD
Pin#
Clock Signals
137
16
76
138
17
75
21
111
Control Signals
157
158
154
65
63
Address Signals
59
52
Name
CK0
NC
CK1
CK2
CK0
NC
CK1
CK2
CKE0
CKE1
NC
S0
S1
NC
RAS
CAS
WE
BA0
BA1
Configuration
Pin Configuration
Table 4
(184 pins). The abbreviations
Pin
Type
I
NC
I
I
I
NC
I
I
I
I
NC
I
I
NC
I
I
I
I
I
Buffer
Type
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Table 5
5
and
Figure
Function
Clock Signals 2:0
Note: For clock net loading see block diagram, CK0 is
Complement Clock Signals 2:0
Note: For clock net loading see block diagram, CK0 is
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
Chip Select Rank 0
Chip Select Rank 1
Note: 2-rank module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
Bank Address Bus 2:0
Table 6
1.
NC on 1R
NC on 1R
respectively. The pin numbering is depicted in
HYS[64/72]D[64/128]3x0EU–[5/6]–D
×
×
Unbuffered DDR SDRAM Modules
16
16
Pin Configuration of UDIMM
Advance Internet Data Sheet
TABLE 4

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