hys64d32301eu-6-d Qimonda, hys64d32301eu-6-d Datasheet - Page 4

• Manufacturer Part Number: hys64d32301eu-6-d
• Description: 184-pin Unbuffered Double-data-rate Memory Modules
• Manufacturer: Qimonda

1.2
The Qimonda HYS64D[64/128]3x0EU-5-D are industry
standard 184-Pin Unbuffered Double-Data-Rate Memory
Modules
64M ×64 (512 MB), 64M ×72 (512 MB), 128M ×72 (1 GB)
and 128M ×64 (1 GB) for non-parity and main memory
applications. The memory array is designed with 512Mbit
Double Data Rate Synchronous DRAMs. A variety of
decoupling
circuit board. The DIMMs feature serial presence detect
Note: All product type numbers end with a place code designating the silicon-die revision. Reference information available on
Rev. 0.60, 2008-05
02142008-4Z51-SEDD
Product Type
PC3200 (CL=3.0)
HYS64D32301EU–5–D
HYS64D64300EU–5–D
HYS72D64300EU–5–D
HYS64D128320EU–5–D
HYS72D128320EU–5–D
PC2700 (CL=2.5)
HYS64D32301EU–6–D
HYS64D64300EU–6–D
HYS72D64300EU–6–D
HYS64D128320EU–6–D
HYS72D128320EU–6–D
Density
256 MB
512 MB
512 MB
1 GB
1 GB
request. Example: HYS72D64300EU-5-D, indicating rev. D dies are used for SDRAM components. The Compliance
Code is printed on the module labels describing the speed sort (for example “PC3200”), the latencies and SPD code
definition (for example “30331” means CAS latency of 3.0 clocks, RCD (Row-Column-Delay) latency of 3 clocks, Row
Precharge latency of 3 clocks, and JEDEC SPD code definiton version 1), and the Raw Card used for this module.
(UDIMM)
Organization
32M ×64
64M ×64
64M ×72
128M ×64
128M ×72
capacitors
Description
organized
are
Memory
Ranks
1
1
1
2
2
Compliance Code
PC3200U–30331–C2
PC3200U–30331–A0
PC3200U–30331–A0
PC3200U–30331–B0
PC3200U–30331–B0
PC3200U–30331–C2
PC2700U–25331–A0
PC2700U–25331–A0
PC2700U–25331–B0
PC2700U–25331–B0
mounted
as
32Mx64
SDRAM
Organization
512M ×16
512M ×8
512M ×8
512M ×8
512M ×8
on
the
(256MB),
printed
# of
SDRAMs
4
8
8
16
16
Description
one rank 256MB DIMM
one rank 512 MB DIMM
one rank 512 MB DIMM ECC
two rank 1GB DIMM
two rank 1GB DIMM ECC
one rank 256MB DIMM
one rank 512 MB DIMM
one rank 512 MB DIMM ECC
two rank 1GB DIMM
two rank 1GB DIMM ECC
4
(SPD) based on a serial E
protocol.
configuration data and the second 128 bytes are available to
the customer.
# of row/bank/
columns bits
13/2/10
13/2/11
13/2/11
13/2/11
13/2/11
The
first
HYS[64/72]D[64/128]3x0EU–[5/6]–D
Unbuffered DDR SDRAM Modules
128 bytes
2
PROM device using the 2-pin I2C
Refresh
8K
8K
8K
8K
8K
Advance Internet Data Sheet
SDRAM Technology
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×16)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
512 Mbit (×8)
Ordering Information
are
64 ms
64 ms
64 ms
64 ms
64 ms
Period
Address Format
programmed
TABLE 2
TABLE 3
7.8 ms
7.8 ms
7.8 ms
7.8 ms
7.8 ms
Interval
with