k9f1208u0c Samsung Semiconductor, Inc., k9f1208u0c Datasheet - Page 34
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k9f1208u0c
Manufacturer Part Number
k9f1208u0c
Description
Flash Mem Parallel 3.3v 512m-bit 64m X 8 48-pin Tsop-i T/r
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K9F1208U0C.pdf
(38 pages)
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K9F1208U0C
K9F1208R0C
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. If the device is already in reset state a new reset command will be
accepted by the command register. The R/B pin changes to low for tRST after the Reset command is written. Refer to Figure 16
below.
Figure 16. RESET Operation
Table 5. Device Status
R/B
I/O
X
Operation mode
FFh
K9F1208B0C
00h Command is latched
After Power-up
t
RST
34
Waiting for next command
After Reset
FLASH MEMORY