mt9htf12872pky Micron Semiconductor Products, mt9htf12872pky Datasheet - Page 13

• Manufacturer Part Number: mt9htf12872pky
• Description: Ddr2 Sdram Mini-rdimm
• Manufacturer: Micron Semiconductor Products

Table 10: I
Values are for the MT47H128M8 DDR2 SDRAM components only, and are computed from values specified in the 1Gb (128
Meg x 8) component data sheet
PDF: 09005aef817ab1fc
htf9c64_128x72pky.pdf - Rev. E 3/10 EN
Parameter/Condition
Operating one bank active-precharge current;
t
tween valid commands; Address bus inputs are switching; Data bus
inputs are switching
Operating one bank active-read-precharge current; I
BL = 4, CL = CL (I
t
valid commands; Address bus inputs are switching; Data pattern is
same as I
Precharge power-down current; All device banks idle;
(I
Data bus inputs are floating
Precharge quiet standby current; All device banks idle;
(I
are stable; Data bus inputs are floating
Precharge standby current; All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are
switching; Data bus inputs are switching
Active power-down current; All device banks
open;
address bus inputs are stable; Data bus inputs are float-
ing
Active standby current; All device banks open;
=
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
Operating burst write current; All device banks open, continuous
burst writes; BL = 4, CL = CL (I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Operating burst read current; All device banks open, continuous
burst reads, I
t
tween valid commands; Address bus inputs are switching; Data bus
inputs are switching
Burst refresh current;
t
Other control and address bus inputs are switching; Data bus inputs
are switching
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control
and address bus inputs are floating; Data bus inputs are floating
RC =
RAS MIN (I
RAS =
RFC (I
DD
DD
t
RAS MAX (I
); CKE is LOW; Other control and address bus inputs are stable;
); CKE is HIGH, S# is HIGH; Other control and address bus inputs
t
DD
RC (I
t
DD
CK =
t
RAS MAX (I
) interval; CKE is HIGH, S# is HIGH between valid commands;
DD4W
),
DD
DD
t
RP =
DD
t
CK (I
OUT
),
),
DD
t
Specifications and Conditions – 1GB
t
RAS =
RCD =
),
DD
t
= 0mA; BL = 4, CL = CL (I
DD
RP (I
t
), AL = 0;
RP =
DD
); CKE is LOW; Other control and
),
DD
t
t
RAS MIN (I
RCD (I
t
t
RP =
); CKE is HIGH, S# is HIGH between valid com-
RP (I
t
CK =
t
CK =
DD
t
DD
DD
RP (I
t
CK (I
); CKE is HIGH, S# is HIGH between
); CKE is HIGH, S# is HIGH between
), AL = 0;
DD
t
DD
CK (I
DD
); CKE is HIGH, S# is HIGH be-
); CKE is HIGH, S# is HIGH be-
); REFRESH command at every
DD
DD
t
),
CK =
), AL = 0;
t
RC =
t
CK (I
t
t
RC (I
CK =
512MB, 1GB (x72, SR) 244-Pin DDR2 Mini-RDIMM
t
CK =
t
DD
t
CK =
CK =
DD
),
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
t
CK (I
t
),
RAS =
t
t
OUT
CK (I
CK =
t
t
t
CK (I
t
CK (I
RAS =
CK =
13
DD
= 0mA;
DD
),
t
DD
t
DD
CK
RAS
t
),
t
CK
RAS
);
),
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
-80E
-800
1440
1440
2115
810
990
450
450
360
540
63
90
63
-667
1215
1215
1935
765
900
360
360
270
495
63
90
63
© 2005 Micron Technology, Inc. All rights reserved.
I
DD
-53E
1125
1125
1890
630
855
360
360
270
405
63
90
63
Specifications
-40E
1845
630
810
315
315
270
360
945
945
63
90
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA