mt16htf25664az Micron Semiconductor Products, mt16htf25664az Datasheet - Page 9

• Manufacturer Part Number: mt16htf25664az
• Description: 2gb, 4gb X64, Dr 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

I
Table 9:
PDF: 09005aef83b82bc1/Source: 09005aef83b82ba5
HTF16C256_512x64AZ.fm - Rev. B 10/09 EN
Parameter/Condition
Operating one bank active-precharge current:
t
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
inputs are switching; Data pattern is the same as I
Precharge power-down current: All device banks idle;
Other control and address bus inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
Precharge standby current: All device banks idle;
HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
Active power-down current: All device banks open;
t
are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus inputs are
switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst reads;
I
t
are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads;
I
t
valid commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
DD
OUT
OUT
RAS =
RCD =
CK =
RAS =
RP =
RC =
Specifications
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
t
t
t
RP (I
RC (I
CK (I
t
t
t
RAS MIN (I
RAS MAX (I
RCD (I
DD
DD
DD
DD
), AL = 0;
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
),
DDR2 I
Values are for the MT47H128M8 DDR2 SDRAM only and are computed from values specified in the
1Gb (128 Meg x 8) component data sheet
); CKE is LOW; Other control and address bus inputs
DD
t
RRD =
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus
DD
), AL = 0;
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
t
),
Notes: 1. Value calculated as one module rank in this operating condition; all other module ranks in
CK =
DD
t
RRD (I
t
RP =
t
CK =
Specifications and Conditions – 2GB
t
CK (I
t
DD
DD
CK =
2. Value calculated reflects all module ranks in this operating condition.
t
DD
RP (I
t
CK (I
), AL = 0;
), AL =
),
I
DD
DD2P
t
t
RCD =
DD
),
CK (I
DD
t
); CKE is HIGH, S# is HIGH between valid
RC =
(CKE LOW) mode.
); REFRESH command at every
t
RCD (I
DD
t
t
CK =
RCD (I
),
t
RC (I
t
RAS =
DD
t
CK (I
) - 1 ×
DD
DD
t
DD4W
),
); CKE is HIGH, S# is HIGH between
CK =
t
t
t
RAS MAX (I
t
DD
CK =
CK =
RAS =
2GB, 4GB (x64, DR): 240-Pin DDR2 SDRAM UDIMM
t
),
CK (I
t
CK (I
t
t
RAS =
t
CK =
t
OUT
CK (I
CK (I
t
t
DD
CK =
RAS MIN (I
9
DD
);
= 0mA; BL = 4,
t
DD
DD
DD
CK (I
),
t
t
RAS MAX (I
CK =
t
),
CK (I
); CKE is HIGH, S# is
),
t
t
RC =
DD
RP =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
RFC (I
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
CK (I
DD
); CKE is LOW;
); CKE is
t
),
t
RC (I
RP (I
DD
DD
DD
)
),
DD
),
DD
),
);
Symbol -1GA
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
I
DD2P
DD3P
DD0
DD1
DD5
DD6
DD7
Electrical Specifications
1
1
2
2
1
2
2
1
2
2
2
1
©2009 Micron Technology, Inc. All rights reserved.
1096
1120
1736
1736
4240
3456
976
112
960
960
800
160
112
-80E/
-800
1336 1136
1336 1136
3760 3440
2736 2296
776
936
112
800
800
640
160
960
112
-667 Unit
736
856
112
640
640
480
160
880
112
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA