mt18ld472ag-5 Micron Semiconductor Products, mt18ld472ag-5 Datasheet
mt18ld472ag-5
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mt18ld472ag-5 Summary of contents
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... PC -6 110ns 60ns 35ns NOTE: Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 – Rev. 6/98 MT9LD272A(X), MT18LD472A(X) For the latest data sheet revisions, please refer to the Micron Web site: www ...
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... OBSOLETE PART NUMBERS EDO Operating Mode PART NUMBER CONFIGURATION MT9LD272AG Meg x 72 ECC MT9LD272AG Meg x 72 ECC MT18LD472AG Meg x 72 ECC MT18LD472AG Meg x 72 ECC FPM Operating Mode PART NUMBER CONFIGURATION MT9LD272AG-6 2 Meg x 72 ECC MT18LD472AG-6 4 Meg x 72 ECC ...
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OBSOLETE together with SA(2:0), which provide eight unique DIMM/ EEPROM addresses. SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and ...
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OBSOLETE DQ0-DQ7 WE0# WE# U1 OE0# OE# RAS0# RAS# CAS0# CAS# A0–A10 CAS1# 11 CAS2# CAS3# A0-A10 DQ32-DQ39 DQ0-DQ7 WE2# WE# U6 OE2# OE# RAS2# RAS# CAS4# CAS# A0–A10 CAS5# 11 CAS6# CAS7# SPD SCL SDA ...
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OBSOLETE DQ0-DQ3 DQ4-DQ7 DQ0-DQ3 DQ0-DQ3 WE0# WE# WE OE0# OE# OE# RAS0# RAS# RAS# CAS0# CAS# A0–A10 CAS# A0–A10 CAS1 CAS2# CAS3# A0-A10 DQ32-DQ35 DQ36-DQ39 DQ0-DQ3 DQ0-DQ3 WE2# WE# WE# U10 U11 OE2# OE# OE# RAS2# ...
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... Ground. SS SDA Input/Output Serial Presence-Detect Data. SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. SCL Input Serial Clock for Presence-Detect. SCL is used to synchronize the presence-detect data transfer to and from the module. ...
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... RESERVED 62 SPD REVISION 63 CHECKSUM FOR BYTES 0-62 64 MANUFACTURER’S JEDEC ID CODE 65-71 MANUFACTURER’S JEDEC CODE (CONT.) 72 MANUFACTURING LOCATION 73-90 MODULE PART NUMBER (ASCII) 91 PCB IDENTIFICATION CODE 92 IDENTIFICATION CODE (CONT.) 93 YEAR OF MANUFACTURE IN BCD 94 WEEK OF MANUFACTURE IN BCD 95-98 MODULE SERIAL NUMBER 99-125 MANUFACTURE SPECIFIC DATA (RSVD) NOTE: 1. “ ...
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OBSOLETE ABSOLUTE MAXIMUM RATINGS* Voltage on V Pin Relative Voltage on Inputs or I/O Pins Relative to V ................................................ -1V to +4.6V SS Operating Temperature, T (ambient) .......... + Storage Temperature ...
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OBSOLETE I OPERATING CONDITIONS AND MAXIMUM LIMITS CC (Notes +3.3V 0.3V) DD PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS STANDBY CURRENT: CMOS (RAS# = CAS 0.2V) DD OPERATING ...
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OBSOLETE CAPACITANCE PARAMETER Input Capacitance: A0-A10 Input Capacitance: WE0#, WE2#, OE0#, OE2# Input Capacitance: RAS0#, RAS2# Input Capacitance: CAS0#-CAS7# Input Capacitance: SCL, SA0-SA2 Input/Output Capacitance: DQ0-DQ63, CB0-CB7, SDA FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes ...
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OBSOLETE FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes 12, 29 +3.3V 0.3V CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay ...
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OBSOLETE EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes 12, 29 +3.3V 0.3V CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER Access time from column address Column-address setup to CAS# precharge Column-address hold ...
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OBSOLETE EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes 12, 29 +3.3V 0.3V CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER RAS# to CAS# precharge time READ command hold time (referenced to RAS#) ...
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OBSOLETE SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS (Notes +3.3V 0.3V) DD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA OUT INPUT LEAKAGE CURRENT: ...
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... With the FPM option, RAS# or CAS# signal to transition HIGH. In compari- t RAD son, latter of the RAS# and CAS# signals to transition t RAD (MAX) HIGH. 27. Applies to both FPM and EDO modules MEG x 72 NONBUFFERED DRAM DIMMs t t RAC and CAC no longer applied). With or t ...
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OBSOLETE NOTES (continued) 28. The SPD EEPROM WRITE cycle time ( time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit are ...
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OBSOLETE V IH RAS CRP V CAS ASR V IH ADDR WE OE FAST PAGE MODE AND EDO ...
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OBSOLETE V IH RAS CRP CAS ASR V IH ADDR ROW IOH DQ V IOL FAST PAGE MODE AND ...
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OBSOLETE V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR V ROW WE IOH DQ OPEN V IOL V IH ...
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OBSOLETE V IH RAS CSH t CRP V CAS RAD t ASR t RAH V IH ADDR V ROW OPEN ...
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OBSOLETE FAST/EDO-PAGE-MODE EARLY WRITE CYCLE V IH RAS CSH t CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WCS ...
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OBSOLETE (LATE WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS ASR V IH ADDR V ROW WE IOH DQ V IOL V IH OE# V ...
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OBSOLETE FAST/EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles RAS CRP V IH CAS RAD t ASR t RAH V IH ADDR ROW WE IOH ...
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OBSOLETE EDO-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP t RCD V IH CAS RAD t ASR t RAH V IH ROW ADDR WE IOH DQ ...
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OBSOLETE FAST-PAGE-MODE READ EARLY WRITE CYCLE V IH RAS CRP V IH CAS ASR V IH ADDR V ROW WE OE# V ...
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OBSOLETE V IH RAS CRP V CAS ASR V IH ROW ADDR WE OE EDO PAGE MODE TIMING ...
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OBSOLETE V IH RAS CRP V IH CAS ASR V IH ADDR WE RAS RPC t ...
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OBSOLETE V IH RAS CRP V IH CAS ASR t RAH V IH ADDR ROW IOH DQ V IOL FAST PAGE MODE AND EDO PAGE MODE ...
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OBSOLETE SCL t SU:STA SDA IN SDA OUT SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL BUF HD:DAT t HD:STA 2, 4 Meg x 72 Nonbuffered DRAM DIMMs DM60.p65 – Rev. 6/98 SPD EEPROM ...
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OBSOLETE .079 (2.00) R (2X) .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 2.625 (66.68) PIN 1 (PIN 85 on backside) .079 (2.00) R (2X) .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP PIN 1 ...