mt18hvf25672pdy-800 Micron Semiconductor Products, mt18hvf25672pdy-800 Datasheet - Page 4
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mt18hvf25672pdy-800
Manufacturer Part Number
mt18hvf25672pdy-800
Description
1gb, 2gb X72, Ecc, Dr 240-pin Ddr2 Sdram Vlp Rdimm
Manufacturer
Micron Semiconductor Products
Datasheet
1.MT18HVF25672PDY-800.pdf
(17 pages)
Table 6:
PDF: 09005aef8286b286/Source: 09005aef8286b2d2
HVF18c128_256x72D.fm - Rev. A 4/07 EN
RAS#, CAS#, WE#
DQS0#–DQS17#
(DQS9–DQS17)
DQS0–DQS8,
ODT0, ODT1
CKE0, CKE1
DQ0–DQ63
DM0–DM8
CK0, CK0#
V
BA0–BA2
SA0–SA2
CB0–CB7
Symbol
E
S0#, S1#
A0–A15
RESET#
DD
V
P
RR
AR
SDA
V
DDSPD
SCL
Vss
/V
_O
REF
_I
DD
N
UT
Q
Pin Descriptions
(LVCMOS)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
Output
Supply
Supply
Supply
Supply
(open
drain)
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
I/O
On-die termination: ODT1 (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS,
DQS#, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Bank address inputs: BA0–BA2 define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA2 define which mode register,
including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE command.
BA0–BA1 (1GB), BA0–BA2 (2GB).
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of
the memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA2) or all device banks (A10 HIGH). The address inputs also provide the
op-code during a LOAD MODE command. A14, A15 connected for parity.
Parity bit for the address and control bus.
Serial clock for presence-detect: SCL is used to synchronize the presence-detect data
transfer to and from the module.
Presence-detect address inputs: These pins are used to configure the presence-detect
devices.
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be
used during power-up to ensure that CKE is LOW and DQs are High-Z.
Data strobe: Output with read data, input with write data for source-synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only
used when differential data strobe mode is enabled via the LOAD MODE command.
Data input mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with that input data, during a write access. DM is sampled on
both edges of DQS. Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins. If RDQS is disabled, DQS9–DQS17 become DM0–DM8 and
DQS9#–DQS17# are not used.
Data input/output: Bidirectional data bus.
Check bits.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and
data into and out of the presence-detect portion of the module.
Parity error found on the address and control bus.
Power supply: 1.8V ±0.1V.
SSTL_18 reference voltage.
Ground.
Serial EEPROM positive power supply: +1.7V to +3.6V.
1GB, 2GB (x72, ECC, DR) 240-Pin DDR2 SDRAM VLP RDIMM
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
Pin Assignments and Descriptions
©2007 Micron Technology, Inc. All rights reserved.