mt18htf25672ay-80e Micron Semiconductor Products, mt18htf25672ay-80e Datasheet - Page 5

• Manufacturer Part Number: mt18htf25672ay-80e
• Description: 512mb, 1gb, 2gb, 4gb X72, Dr, Ecc 240-pin Ddr2 Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 8:
PDF: 09005aef80e8ad4d/Source: 09005aef80e785e6
HTF18C64_128_256_512x72A.fm - Rev. H 5/08 EN
RAS#, CAS#, WE#
BA0, BA1, BA2
DQS0#–DQS8#
(512MB, 1GB)
DQS0–DQS8,
ODT0, ODT1
CKE0, CKE1
DQ0–DQ63
CK0, CK0#,
CK1, CK1#,
(2GB, 4GB)
(1GB, 2GB)
DM0–DM8
CK2, CK2#
V
BA0, BA1
SA0–SA2
CB0–CB7
Symbol
(512MB)
S0#, S1#
A0–A12
A0–A13
A0–A14
DD
V
(4GB)
SDA
V
DDSPD
RFU
SCL
V
NC
/V
REF
SS
DD
Q
Pin Descriptions
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
–
–
512MB, 1GB, 2GB, 4GB (x72, DR, ECC) 240-Pin DDR2 SDRAM UDIMM
On-die termination: ODT (registered HIGH) enables termination resistance internal to
the DDR2 SDRAM. When enabled, ODT is only applied to the following pins: DQ, DQS,
DQS#, and CB. The ODT input will be ignored if disabled via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of CK#. Output
data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE
command.
Address inputs: Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of
the memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA0–BA1/BA2) or all device banks (A10 HIGH). The address inputs also provide
the op-code during a LOAD MODE command.
Serial clock for presence-detect: SCL is used to synchronize the presence-detect data
transfer to and from the module.
Presence-detect address inputs: These pins are used to configure the presence-detect
device.
Data input mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with that input data, during a write access. DM is sampled on
both edges of DQS. Although DM pins are input-only, the DM loading is designed to
match that of DQ and DQS pins.
Data strobe: Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only
used when differential data strobe mode is enabled via the LOAD MODE command.
Data input/output: Bidirectional data bus.
Check bits.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses and
data into and out of the presence-detect portion of the module.
Power supply: 1.8V ±0.1V.
SSTL_18 reference voltage.
Ground.
Serial EEPROM positive power supply: +1.7V to +3.6V.
No connect: These pins should be left unconnected.
Reserved for future use.
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Description
Pin Assignments and Descriptions
©2003 Micron Technology, Inc. All rights reserved.