m69aw024b STMicroelectronics, m69aw024b Datasheet
m69aw024b
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m69aw024b Summary of contents
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... FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIME: 60ns, 70ns LOW STANDBY CURRENT: 70µA DEEP POWER DOWN CURRENT: 10µA LOW V DATA RETENTION: 2.3V CC COMPATIBLE WITH STANDARD LPSRAM September 2004 16 Mbit (1M x16) 3V Asynchronous PSRAM Figure 1. Package M69AW024B BGA TFBGA48 (ZB) 6x8 mm 1/29 ...
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... M69AW024B TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A19 Data Inputs/Outputs (DQ8-DQ15 Data Inputs/Outputs (DQ0-DQ7 Chip Enable (E1 Chip Enable (E2 Output Enable (G Write Enable (W) ...
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... Data Retention AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CC PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 24.TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Outline, Bottom View . . . . 26 Table 11. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Mechanical Data PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 12. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 REVISION HISTORY Table 13. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 M69AW024B 3/29 ...
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... M69AW024B SUMMARY DESCRIPTION The M69AW024B Mbit (16,777,216 bit) CMOS memory, organized as 1,048,576 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range. M69AW024B is a member of STMicroelectronics PSRAM memory family, based on the one-transis- tor per-cell architecture. These devices are manu- factured using dynamic random access memory ...
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... DQ8 DQ9 A5 A6 DQ10 V SS A17 A7 DQ11 A16 DQ12 DQ14 A14 A15 DQ13 DQ15 A12 A13 A19 A18 A8 A9 A10 M69AW024B DQ0 DQ1 DQ2 DQ3 V CC DQ4 V SS DQ5 DQ6 W DQ7 A11 NC AI07409 5/29 ...
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... M69AW024B SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, 1., Signal Names, for a brief overview of the sig- nals connected to this device. Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access dur- ing Read and Write operations. Data Inputs/Outputs (DQ8-DQ15). The ...
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... Figure 4. Block Diagram INTERNAL GENERATOR ADDRESS CONTROL CONTROLLER V SS ARBITRATION LOGIC CLOCK REFRESH CONTROLLER DYNAMIC MEMORY ARRAY INPUT/OUTPUT BUFFER COLUMN DECODER LOGIC ADDRESS POWER M69AW024B V CC DQ0-DQ7 DQ8-DQ15 AI07410 7/29 ...
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... M69AW024B Table 2. Operating Modes Operation E2 E1 Standby (Deselect ( Output Disabled IH IL Output Disabled (No Read Word Read( Word Read Upper Byte Write IH IL Lower Byte Write Word Write ...
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... Operational modes are determined by device con- trol inputs W, E1, E2, LB and UB as summarized in the Operating Modes table (see Power On Sequence Because the internal control logic M69AW024B needs to be initialized, the following power-on procedure must be followed before the memory is used: – Apply power and wait for V – ...
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... M69AW024B MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause per- manent damage to the device. Exposure to Abso- lute Maximum Rating conditions for extended periods may affect device reliability. These are Table 3. Absolute Maximum Ratings ...
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... and Figure 6. AC Measurement I/O Waveform I/O Timing Reference Voltage V CC OUT 0V Output Timing Reference Voltage AI07222c M69AW024B Table 4., Operating and Conditions. Designers should M69AW024B –60, –70 Max Table 9. Unit V °C ...
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... M69AW024B Table 5. Capacitance Symbol C Input Capacitance on all pins (except DQ) IN (1) Output Capacitance C OUT Note: 1. Outputs deselected. Table 6. DC Characteristics Symbol Parameter Operating Supply (1) I CC1 Current Input Leakage I LI Current Output Leakage I LO Current Deep Power Down I PD Current Standby Supply ...
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... Output Enable High to Output Hi-Z t OHZ GHQZ (4,9) t Output Enable Low to Address Hold Time t OLAH GLAX (9) t Output Enable Low to Chip Enable High Delay Time t OLCH GLEH Parameter M69AW024B M69AW024B –60 –70 Unit Min Max Min Max –5 – ...
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... ELGL AVAX 10. The maximum value is applicable kept Low. 14/29 Parameter is increased by the difference between the actual value and the spec- GLQV is lower than the specified minimum value, t GHGL1 (Actual), respectively. GHGL1 M69AW024B –60 –70 Unit Min Max Min Max ...
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... ADDRESS VALID ADDRESS VALID tGHAX tELGH tELQV tGLQV tGHGL1 tGHBH tGHQZ tGHQX VALID ADDRESS VALID tELEH tEHAX tELQV tEHBH tEHQZ tEHQX VALID M69AW024B tGHAX tAVGH tAVGL2 tGLEH tGLQV tBLGL tGHBH tGHQZ tGLQX tGHQX VALID AI07743 ADDRESS VALID tELEH tAVEL tELQV tEHAX tEHEL ...
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... M69AW024B Figure 9. Address Access After G Control, Read Mode AC Waveforms A3-A19 A0-A2 tAVGL1 E1 G tBLGL LB, UB tGLQX DQ0-DQ15 Note High and W = High. 2. Either or both LB and UB must be Low when both E1 and G are Low. Figure 10. Address Access After E1 Control, Read Mode AC Waveforms A3-A19 A0-A2 tAVEL ...
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... Write Enable Write Recovery Time to Write Enable (1,3,9,10 WHWL Low t t Write Enable Low to Address Valid Write Cycle Time WLAV WC (2) t Address Hold Time from Write Enable Low t AH WLAX Parameter M69AW024B M69AW024B –60 –70 Unit Min Max Min Max 1000 35 1000 ns 12 ...
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... Parameter ELEH (Min) and is a reference value when access time is determined by t AVAX is increased by the difference between the actual value and the specified minimum AXGL1 (min) is also applied. Table 7., Read and Standby Modes AC M69AW024B –60 –70 Min Max Min ...
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... VALID DATA INPUT ADDRESS VALID tAVWL tWLAX tELWL tWLWH tBLWL tGHWL tGHQZ VALID DATA INPUT M69AW024B ADDRESS VALID tAVEL tEHEL1 tWLEL tBLEL tEHDX tWLWL ADDRESS VALID tAVWL tWHEH tEHEL2 tWHWL tWHBH tDVWH tWHDX AI07411C ...
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... M69AW024B Figure 13. W Controlled, Continuous Write AC Waveforms ADDRESS VALID A0-A19 tGHAX E1 tGHEL W tGHBH UB tGHQZ DQ0-DQ15 Note must be High during the Write cycle. Figure 14. E1 Controlled, Read/Write AC Waveforms ADDRESS VALID A0-A19 tEHAX E1 tEHWL W tEHBH UB tEHQZ tEHQX DQ0-DQ15 READ DATA OUTPUT Note: 1 ...
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... READ DATA OUTPUT tWLAV WRITE ADDRESS tAVWL tWLAX tWLWH tBLWL tGHWL tDVWH WRITE DATA INPUT M69AW024B WRITE ADDRESS tEHAX tAVEL tEHEL1 tEHWL tWLEL tEHBH tBLEL tGHEL tEHQZ tEHQX AI07415C READ ADDRESS tAVGL1 tWHAV tWHBH ...
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... M69AW024B Figure 17. G Controlled Read, W Controlled Write AC Waveforms 2 A0-A19 E1 Low tWHAV W tWHBH UB tWHDX WRITE DATA INPUT DQ0-DQ15 Note can be tied to Low for W and G controlled operation. When E1 is tied to Low, output is exclusively controlled by G. 22/29 tAVGH READ ADDRESS tAVGL1 tGHAX tBLGL ...
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... Stand-by mode. If either of timing is not satisfied, it takes the t EHGH EHWH from either the last address transition of A0, A1 and A2 rising edge. Parameter is less than the minimum required time. EHWH . CHCL E1 tEHGH G W Standby M69AW024B M69AW024B –60 –70 Min Max Min Max 350 350 400 400 ...
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... M69AW024B Figure 19. Power-down AC Waveforms E1 E2 Hi-Z DQ Note: This Power Down mode can be also be used in “Power-up Mode AC Waveforms - 2”. Figure 20. Power-up Mode AC Waveforms - Note: t starts from V reaching V VHCH CC Figure 21. Power-up Mode AC Waveforms - Note: t starts from V reaching V VHCL ...
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... Test Condition –0.2V and OUT 0.2V. IL DATA RETENTION MODE and – 0. (min) Data Bus must be Hi-Z M69AW024B 1 Min V –0.2V 2.3 and 0. –0.2V –0.2V 0mA 2.7V 0 2.7V 100 0 AI08054C (Figure 20.) ...
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... M69AW024B PACKAGE MECHANICAL Figure 24. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Outline, Bottom View FD FE BALL "A1" Note: Drawing is not to scale. Table 11. TFBGA48 6x8mm - 6x8 Ball Array, 0.75mm Pitch, Package Mechanical Data Symbol Typ 6.000 D1 3.750 ...
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... Shipping Method T = Tape & Reel Packing The notation used for the device number is as shown in package, etc.) or for further information on any aspect of this device, please contact your nearest STMi- croelectronics Sales Office. M69AW024 Table 12. For a list of available options (speed, M69AW024B 8 T 27/29 ...
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... M69AW024B REVISION HISTORY Table 13. Document Revision History Date Rev. 01-Jun-2002 1.0 First Issue 04-Feb-2003 2.0 Document completely revised 14-Mar-2003 2.1 AC Testing Load Circuit revised; 60ns access time device added 29-Apr-2003 2.2 Timing parameter names changed in tables and illustrations 25-Jul-2003 2.3 Chip enable signals E1 and E2 must change together during Power-on sequence Datasheet title updated ...
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