w86l488 Winbond Electronics Corp America, w86l488 Datasheet - Page 27

• Manufacturer Part Number: w86l488
• Description: Sd/ Sdio/ Mmc Memory Card Bridge
• Manufacturer: Winbond Electronics Corp America

7.2 Card Inserting and Removing
There are two method for Host to detect SD/SDIO or MMC card inserting or removing through
W86L488, the first method is detected by CD/DAT3 pin, the second method is a dedicate switch on
the SD/MMC slot can be connected to the GIO0 pin and set GIO0 to input direction. These two
methods can be performed even if the W86L488 is in power down state.
Method 1, CD/DAT3 as card detection:
The CD/DAT3 of SD bus can be used as card detection if no data transfer on the DAT3, if SIEN bit of
the control register is low and CD_IE and INT_E on the interrupt enable register are all high, card
inserting or removing will generate interrupt. Host must read the interrupt status register and re-check
the card state by read the CD bit on the extend status register. This detection method will not effective
when wide bus on the SD bus is transfer. MMC card may not support this detection method.
Method 2, GIO0, GIP6 as card detection (inserting):
Some SD/MMC slot support external switch for card existing detection, the switch will on when
SD/SDIO or MMC card is exist. GIO0 and GIP6 with a pull high resister can be used as card detection
of port A and port B. In port A the Host can disable the GOEN0 bit on the general I/O port control
register and enable the GIT_EN0 bit on the general I/O port interrupt enable register and enable
GIT_IE and INT_E bits on the interrupt enable register. SD or MMC card inserting or removing will
change the switch state then change the state of GIO0 pin and then generate interrupt to the Host.
Host may re-check the card state by read the GIN0 bit on the general I/O port data register. The card
insert status of port A and port B also can be read in the global status and control register.
Figure 7-10 shows the waveform of GIO0 and GIOx when card insert and remove if GIO0 as card
insert and GIOx as write protect input.
XWRHN
XINTN
System_
A[3:1]
D[15:0]
XCSN
XRDN
Clock
Fig. 7-10 Timing of Interrupt in (XINTN pin goes to low again).
011
0x90XX
- 24 -
011
Publication Release Date: February 5, 2004
Preliminary W86L488
1xx0xxxxb
Revision 0.82