w86l488 Winbond Electronics Corp America, w86l488 Datasheet - Page 25

• Manufacturer Part Number: w86l488
• Description: Sd/ Sdio/ Mmc Memory Card Bridge
• Manufacturer: Winbond Electronics Corp America

Data Access Request:
Data access request XDRQN is used to notify the Host that the Host should write data to the transmit
data buffer or read data from the receive data buffer in data write to the card or data read from the
card. The Data access request action also effective when Host interface type 2 is selected.
During data transmit to the card, the XDRQN will active if the data write command has been transfer
to the card and the transmit data buffer have not enough data to transmit to the card. The XDRQN will
not active if the transmit data buffer have enough data to transmit to the card. The last byte of the data
should placed at bit [15:8] if the data length is odd byte and CPU data size is 16-bit.
During data receive from the card, the XDRQN will active if the data read command has been transfer
to the card and the data have been received in the receive data buffer. The XDRQN will not active if
the data read command has been executed completedly and the receive data buffer is read out. The
last byte of the data is located at bit [7:0] if the data length is odd byte and CPU data size is 16-bit.
There are two types of data access request waveform, one is single access mode and the other is
burst access mode. Single access mode is configured if DABST = low, XDRQN will inactive after each
access receive or transmit data buffer, the XDRQN will re-active after four clock later. Figure 7-7
shows the waveform of Host access receive data buffer in single access mode (DABST = low). Burst
access mode is configured if DABST = high, XDRQN will hold at active state until the data has been
transferred completedly. The Host can access receive or transmit data buffer with higher speed
continuously and regardless of the system clock. Figure 7-8 is the waveform of Host access transmit
data buffer in burst mode (DABST = high).
Fig. 7-7 Host Read Receive Data Buffer in Single Access Mode (DABST = low).
A[3:1]
D[15:0]
XCSN
XRDN
XDRQN
System
Clock
010
- 22 -
Publication Release Date: February 5, 2004
Preliminary W86L488
010
Revision 0.82