hb28d032bp2 Renesas Electronics Corporation., hb28d032bp2 Datasheet - Page 49

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hb28d032bp2

Manufacturer Part Number
hb28d032bp2
Description
Mobile Embedded Flash With Multimediacard-tm Interface 16 Mbyte/32 Mbyte
Manufacturer
Renesas Electronics Corporation.
Datasheet
The host command and the card response are clocked out with the rising edge of the host clock. The delay
between host command and card response is N
for host command CMD3:
There is just one Z bit period followed by P bits pushed up by the responding card. The following timing
diagram is relevant for all host commands followed by a response, except CMD1, CMD2 and CMD3:
The card identification (CMD2) and card operation condition (CMD1) timing are processed in the open-
drain mode. The card response to the host command starts after exactly N
After receiving the last card response, the host can start the next command transmission after at least N
clock cycles. This timing is relevant for any host command.
Card identification and card operation conditions timing
Last card response - next host command timing
CMD
CMD
CMD
CMD
S T
S T
S T
S T
Timing Response End to Next CMD Start (Data Transfer Mode)
Host command
Host command
Host active
Host active
Host command
content
content
Host active
Command Response Timing (Data Transfer Mode)
content
Command Response Timing (Identification Mode)
Card active
Identification Timing (Card Identification Mode)
content
Response
CRC E Z
CRC E Z Z P
CRC E Z
CRC E Z
CR
N
N
N
* * * * * *
CR
CR
clock cycles. The following timing diagram is relevant
ID
N
* * *
cycles
cycles
cycles
* * * * * *
RC
* * *
cycles
P
Z
Z
S T
S T
S T
Card active
Z
S T
Card active
Card active
Response
Response
content
content
CID or OCR
Host command
ID
content
content
Host active
clock cycles.
HB28E016/D032BP2
CRC E Z Z Z
CRC E Z Z Z
CRC E
Z Z Z
49
RC

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