ic42s16400a ETC-unknow, ic42s16400a Datasheet - Page 3
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ic42s16400a
Manufacturer Part Number
ic42s16400a
Description
1m X 16bit X 4 Banks 64-mbit Sdram
Manufacturer
ETC-unknow
Datasheet
1.IC42S16400A.pdf
(67 pages)
- Current page: 3 of 67
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IC42S16400A
60-BALL VF-BGA ( 64M SDRAM )
PIN DESCRIPTIONS
Integrated Circuit Solution Inc.
DR039-0A 02/19/2004
A0 - A11
BA0,BA1
DQ0 - DQ15
CLK
CKE
CS
RAS
CAS
WE
LDQM,UDQM
V
V
NC
DD
DD
/V
Q/V
7
6
5
4
3
2
1
SS
SS
Q
VSS
VDD
A4
R
A3
Data Input/Output
Address
Bank Address
Clock
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Power Supply/Ground
Data Output Power/Ground
No Connection
A6
A5
P
A1
A2
A10
A7
A8
N
A0
BA1
A11
BA0
A9
M
CKE
NC
NC
CS
L
RAS
CLK
CAS
NC
K
Row Address : RA0 - RA11, Column Address : CA0 - CA7
Auto-precharge flag : A10
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Multiplexed data input / output pin
The system clock input.All other inputs are registered to the SDRAM
on the rising edge of CLK
Controls internal clock signal and when deactivated,the SDRAM will
be one of the states among power down,suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
RAS,CAS and WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in write
mode
Power supply for internal circuits and input buffers
Power supply for output buffers
No Connection
UDQM
LDQM
NC
WE
J
VDD
NC
NC
NC
H
DQ8
DQ7
NC
NC
G
VDDQ
DQ9
VSSQ
DQ6
F
VSSQ
DQ
VDDQ
DQ5
E
10
DQ
DQ
DQ4
DQ3
D
12
11
VDDQ
DQ
VSSQ
DQ2
C
13
DQ
V
VSSQ
DQ1
DDQ
B
14
DQ
VSS
VDD
DQ0
A
15
3
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