ic42s16400a ETC-unknow, ic42s16400a Datasheet - Page 23

• Manufacturer Part Number: ic42s16400a
• Description: 1m X 16bit X 4 Banks 64-mbit Sdram
• Manufacturer: ETC-unknow

IC42S16400A
Write to Read Command Interval
The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command
will be written. The data bus must be Hi-Z at least one cycle prior to the first D
WRITE to READ Command Interval
Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
DQM must be in High at least 3 clocks prior to the write command. There is a restriction to avoid a data conflict. The data
bus must be Hi-Z using DQM before Write.
Integrated Circuit Solution Inc.
DR039-0A 02/19/2004
Command
CAS latency=2
DQ
Command
CAS latency=3
DQ
CLK
T0
WRITE A
Write A
DA0
DA0
1 cycle
T1
Read B
Read B
Hi-Z
Hi-Z
T2
T3
QB0
T4
OUT
QB1
QB0
.
T5
QB2
QB1
T6
QB3
QB2
T7
Burst lengh=4
QB3
T8
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