k4s640832n-lc75 Samsung Semiconductor, Inc., k4s640832n-lc75 Datasheet - Page 4

• Manufacturer Part Number: k4s640832n-lc75
• Description: 64mb N-die Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

2M x 8Bit x 4Banks / 1M x 16Bit x 4Banks SDRAM
1.0 FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system clock
• Burst read single-bit write operation
• DQM (x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
• Pb-free and Halogen-free Package
• RoHS compliant
2.0 GENERAL DESCRIPTION
bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows
precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies,
programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
3.0 Ordering Information
K4S640832N
K4S641632N
The K4S640832N / K4S641632N is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 8
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
K4S640832N-LC/L75
K4S641632N-LC/L50
K4S641632N-LC/L60
K4S641632N-LC/L75
Part No.
Organization
4Mx16
8Mx8
Orgainization
Row & Column address configuration
4Mb x 16
8Mb x 8
Row Address
A0~A11
A0~A11
4 of 15
133MHz(CL=3)
200MHz(CL=3)
166MHz(CL=3)
133MHz(CL=3)
Max Freq.
Column Address
A0-A8
A0-A7
Interface
LVTTL
Rev. 1.1 December 2007
Synchronous DRAM
Pb-free & Halogen-Free
54pin TSOP(II)
Package