k4t1g084qc Samsung Semiconductor, Inc., k4t1g084qc Datasheet - Page 21

• Manufacturer Part Number: k4t1g084qc
• Description: 1gb C-die Ddr2 Sdram Specification
• Manufacturer: Samsung Semiconductor, Inc.

4. Differential data strobe
bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode
dependent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at VREF. In differential mode,
these timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by
design and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally
to VSS through a 20 ohm to 10 K ohm resisor to insure proper operation.
5. AC timings are for linear signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They may be guaranteed by device design or tester
7. All voltages are referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
K4T1G044QC
K4T1G084QC
correlation.
specifications and device operation are guaranteed for the full voltage range specified.
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS “Enable DQS” mode
CK/CK
DQS/DQS
DQ
DQS/
DQS
DQ
DM
CK
CK
DQS
DQS
t
CH
t
RPRE
t
DQS
DQS
WPRE
V
V
t
t
CL
IH
DQSQmax
IL
(ac)
(ac)
<Data output (read) timing>
t
DMin
DS
D
<Data input (write) timing>
t
DQSH
V
t
V
QH
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IH
IL
(ac)
(ac)
Q
DMin
t
DS
D
t
DQSL
Q
DMin
D
t
DH
V
V
IH
IL
(dc)
(dc)
t
DQSQmax
Q
DMin
D
t
DH
V
V
IH
IL
t
(dc)
WPST
(dc)
t
t
RPST
QH
Q
DDR2 SDRAM
Rev. 1.1 June 2007