m36l0r7060t1zaqe Numonyx, m36l0r7060t1zaqe Datasheet - Page 14
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m36l0r7060t1zaqe
Manufacturer Part Number
m36l0r7060t1zaqe
Description
128 Mbit Multiple Bank, Multilevel, Burst Flash Memory And 64 Mbit Burst Psram, 1.8 V Supply, Multichip Package
Manufacturer
Numonyx
Datasheet
1.M36L0R7060T1ZAQE.pdf
(22 pages)
Functional description
Table 2.
1. X = Don't care.
2. In the PSRAM, the Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in
3. The PSRAM must have been configured to operate in asynchronous mode by setting BCR15 to ‘1’ (default value).
4. WAIT signal polarity is configured using the Set Configuration Register command. See the M58LR128HTB datasheet for
5. L
6. Depends on G
7. BCR and RCR only.
8. A18 and A19 are used to select the BCR, RCR or DIDR registers.
9. Bit 4 of the Refresh Configuration Register must be set to ‘0’ and E must be maintained High, V
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Flash Read
Flash Write
Flash Address
Latch
Flash Output
Disable
Flash Standby
Flash Reset
PSRAM Read
PSRAM Write
PSRAM
Program
Configuration
Register (CR
Controlled)
PSRAM
Standby
PSRAM Deep
Power-Down
Operation
Standby and Deep Power-Down modes.
details.
Down mode.
F
can be tied to V
(2)(3)
(7)
(9)
Main operating modes
F
V
V
V
V
V
E
.
X
IH
IL
IL
IL
IL
F
IH
The Flash memory must be
Any Flash mode is allowed.
V
V
V
G
if the valid address has been previously latched.
X
X
X
IH
IH
IL
F
W
V
V
V
V
X
X
IH
IH
IH
IL
F
disabled.
V
V
V
L
IL
IL
X
X
X
IL
F
(5)
(5)
RP
V
V
V
V
V
V
IH
IH
IH
IH
IH
IL
(1)
F
WAIT
Hi-Z
Hi-Z
Hi-Z
F
(4)
V
V
V
V
V
E
IH
IH
IL
IL
IL
P
CR
V
V
V
V
X
IH
IL
IL
IL
P
Any PSRAM mode is allowed.
PSRAM must be disabled.
G
V
X
X
X
X
IL
P
W
V
V
V
X
X
IH
IL
IL
P
LB
P
V
V
M36L0R7060T1, M36L0R7060B1
X
X
X
,UB
IL
IL
P
A19 A18
00(RCR)
10(BCR)
X
X
(8)
IH
, during Deep Power-
Valid
Valid
X
X
BCR/
A20-
RCR
Data
A17
A21
A0-
X
X
Flash Data In
Out or Hi-Z
PSRAM data
PSRAM data
DQ15-DQ0
Flash Data
Flash Data
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Out
out
in
(6)